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DQG $WKORQ 70 DUH UHJLVWHUHG WUDGHPDUNV RI $GYDQFHG 0LFUR 'HYLFHV $0'. &HOHURQ 3HQWLXP 3HQWLXP,, 3HQWLXP,,, 00; DQG ,QWHO DUH UHJLVWHUHG WUDGHPDUNV RI ,QWHO &RUS LV D UHJLVWHUHG WUDGHPDUN RI ,QWHUQDWLRQDO %XVLQHVV 0DFKLQHV &RUS 36 DUH UHJLVWHUHG WUDGHPDUNV RI 0LFURVRIW &RUS :LQGRZV :LQGRZV DQG 3OXJ DQG 3OD\ LV D UHJLVWHUHG WUDGHPDUN RI WKH 3&, 6SHFLDO ,QWHUHVW *URXS 3&, LV D WUDGHPDUN RI WKH 9LGHR (OHFWURQLFV 6WDQGDUGV $VVRFLDWLRQ 9(6$ 9,$ 7HFKQRORJLHV WK )ORRU 1R 1 &KXQJ&KHQJ 5RDG +VLQ7LHQ 7DLSHL 7DLZDQ 52& 7HO )D[ 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A REVISION HISTORY Document Release 0.1 Date 10/9/00 Revision Created from VT8363 data sheet rev 1.0 Fixed typographical errors in GPIPE# and GRBF# pin descriptions Removed FPG/EDO information Updated Device 0 register descriptions: Rx8, 54[5-4], 55[4], 56-58, 60, 63[10], 67, 68[7,4-3,1-0], 69[7-6], 6C[5-4], 76[5-4], 79[7-3,0], 7B, 80[15-8], AC[6], AD[6-5], AF, B0[7], B2[3], B3, B5, B6[6-5], B8, F6 Updated Device 1 register descriptions: Rx2, 34, 44[5] Removed ambient temp spec and changed case operating temp spec to 85 C Created separate table for power specs Fixed pin 1 orientation in mechanical diagram Initials DH Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -i- 1 Revision History 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A TABLE OF CONTENTS REVISION HISTORY........................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES..........................................................................................................................................................................III LIST OF TABLES ...........................................................................................................................................................................IV KT133A AMD ATHLONTM NORTH BRIDGE .............................................................................................................................. 1 PINOUTS .......................................................................................................................................................................................... 6 PIN DESCRIPTIONS ........................................................................................................................................................................ 9 REGISTERS ..................................................................................................................................................................................... 17 REGISTER OVERVIEW ................................................................................................................................................................. 17 MISCELLANEOUS I/O................................................................................................................................................................... 21 CONFIGURATION SPACE I/O ....................................................................................................................................................... 21 REGISTER DESCRIPTIONS............................................................................................................................................................ 22 Device 0 Header Registers - Host Bridge............................................................................................................................ 22 Device 0 Configuration Registers - Host Bridge ................................................................................................................ 24 Host CPU Control ................................................................................................................................................................................. 24 DRAM Control ..................................................................................................................................................................................... 25 PCI Bus Control.................................................................................................................................................................................... 30 GART / Graphics Aperture Control ...................................................................................................................................................... 34 AGP Control ......................................................................................................................................................................................... 36 Device 1 Header Registers - PCI-to-PCI Bridge ................................................................................................................ 41 Device 1 Configuration Registers - PCI-to-PCI Bridge..................................................................................................... 43 AGP Bus Control .................................................................................................................................................................................. 43 ELECTRICAL SPECIFICATIONS............................................................................................................................................... 46 ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................. 46 DC CHARACTERISTICS................................................................................................................................................................ 46 POWER CHARACTERISTICS ......................................................................................................................................................... 47 AC TIMING SPECIFICATIONS ...................................................................................................................................................... 47 MECHANICAL SPECIFICATIONS ............................................................................................................................................. 48 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -ii- OVERVIEW ....................................................................................................................................................................................... 4 1 Table of Contents 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. KT133A SYSTEM BLOCK DIAGRAM USING THE VT82C686A SOUTH BRIDGE........................................ 4 VT8363A KT133A BALL DIAGRAM (TOP VIEW) ................................................................................................ 6 CPU / SDRAM / AGP / PCI CLOCK CONNECTIONS ......................................................................................... 15 GRAPHICS APERTURE ADDRESS TRANSLATION ......................................................................................... 34 MECHANICAL SPECIFICATIONS - 552-PIN BALL GRID ARRAY PACKAGE ........................................... 48 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -iiiList of Figures 1 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A LIST OF TABLES TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. TABLE 6. TABLE 7. TABLE 8. VT8363A KT133A PIN LIST (NUMERICAL ORDER)............................................................................................. 7 VT8363A KT133A PIN LIST (ALPHABETICAL ORDER) ...................................................................................... 8 VT8363A KT133A PIN DESCRIPTIONS.................................................................................................................... 9 VT8363A REGISTERS ................................................................................................................................................ 17 SYSTEM MEMORY MAP.......................................................................................................................................... 25 MEMORY ADDRESS MAPPING TABLE ............................................................................................................... 25 VGA/MDA MEMORY/IO REDIRECTION.............................................................................................................. 43 AC TIMING MIN / MAX CONDITIONS.................................................................................................................. 47 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -ivList of Tables 1 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A VIA VT8363A KT133A AMD ATHLONTM NORTH BRIDGE Single-Chip North Bridge for Socket-A (Socket-462) Based Athlon CPUs with 200 / 266 MHz Front Side Bus for Desktop PC Systems with AGP 4x and PCI plus Advanced Memory Controller supporting PC133 / PC100 SDRAM and VCM * High Performance and High Integration Athlon AGP 4x / PC133 Chipset with Advanced System Power Management - KT133A Chipset: VT8363A system controller and VT82C686A PCI to ISA bridge - Single chip Athlon system controller with 64-bit Socket-A Athlon CPU, 64-bit system memory, 32-bit PCI and 32- PCI-to-ISA bridge chip includes UltraDMA-33/66 EIDE, 4 USB Ports, Integrated Super-I/O, AC97 / MC97 link (for - - Audio and Modem support), Hardware Monitoring, Power Management, and Keyboard / PS2-Mouse Interfaces plus RTC / CMOS on chip Supports separately powered 3.3V (5V tolerant) interface to system memory, AGP, and PCI bus Modular power management and clock control for advanced system power management bit AGP interfaces Preliminary Revision 0.1, October 9, 2000 * High Performance Athlon CPU Interface - Supports Socket-A (Socket-462) AMD Athlon processors with 200 and 266 MHz Front Side Bus - HSTL-like 1.5V high-speed transceiver logic signal levels - Independent address, data, and snoop interfaces - 100 and 133 MHz DDR (Double Data Rate) transfer on Athlon CPU address and data buses - Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions - Four-entry command queue to accommodate maximum CPU throughput - Four-entry probe queue to stores probes from the system to the processor - Twenty four-entry processor system data and control queue to store system data control commands in two separate - Supports WC (Write Combining) cycles - Sleep mode support - System management interrupt, memory remap and STPCLK mechanism read and write buffers for data movement in and out of processor interface 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -1- 1 Features 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A * Full Featured Accelerated Graphics Port (AGP) Controller - Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control - - - - - - - - - - - PCI AGP CPU Mode 33 MHz 66 MHz 100 MHz DDR 3x synchronous AGP v2.0 compliant Supports SideBand Addressing (SBA) mode (non-multiplexed address / data) Supports 66 MHz 1x, 2x and 4x modes for AD and SBA signaling Pipelined split-transaction long-burst transfers up to 1GB/sec Thirty-two level read request queue Four level posted-write request queue Thirty-two level (quadwords) read data FIFO (256 bytes) Sixteen level (quadwords) write data FIFO (128 bytes) Intelligent request reordering for maximum AGP bus utilization Supports Flush/Fence commands Graphics Address Relocation Table (GART) - Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support - One level TLB structure - Sixteen entry fully associative page table - LRU replacement scheme * Concurrent PCI Bus Controller - PCI buses are synchronous / pseudo-synchronous to host CPU bus - 33 MHz operation on the primary PCI bus - 66 MHz PCI operation on the AGP bus - PCI-to-PCI bridge configuration on the 66MHz PCI bus - Supports up to five PCI masters - Peer concurrency - Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time - Zero wait state PCI master and slave burst transfer rate - PCI to system memory data streaming up to 132Mbyte/sec - Two lines (32 double-words) of CPU to PCI posted write buffers - Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities - Enhanced PCI command optimization (MRL, MRM, MWI, etc.) - Thirty-two levels (double-words) of post write buffers from PCI masters to DRAM - - - - - - - (two cache lines / 16 double-words for PCI bus, two cache lines / 16 double-words for Athlon processor interface) Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters Delay transaction from PCI master accessing DRAM Read caching for PCI master reading DRAM Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks) Symmetric arbitration between Host/PCI bus for optimized system performance Complete steerable PCI interrupts PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -2- 1 Features 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A - - - - - - - (e.g., precharge other banks while accessing the current bank) Four cache lines (32 quadwords) of CPU to DRAM write buffers Four cache lines (32 quadwords) of CPU to DRAM read prefetch buffers Read around write capability for non-stalled CPU read Burst read and write operation BIOS shadow at 16KB increment Decoupled and burst DRAM refresh with staggered RAS timing CAS before RAS or self refresh * Advanced System Power Management Support - Dynamic power down of SDRAM (CKE) - PCI and AGP bus clock run and clock generator control - VTT suspend power plane preserves memory data - Suspend-to-DRAM and Self-Refresh operation - SDRAM self-refresh power down - 8 bytes of BIOS scratch registers - Low-leakage I/O pads * Built-in NAND-tree pin scan test capability * 35 x 35 mm, 552 pin BGA Package Preliminary Revision 0.1, October 9, 2000 1 * 3.3V, 0.35um, high speed / low power CMOS process 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -3- * Advanced High-Performance DRAM Controller - Supports PC133 and PC100 SDRAM and Virtual Channel Memory (VCM) SDRAM up to 3 DIMMs - Concurrent CPU, AGP, and PCI access - Different DRAM types may be used in mixed combinations - Different DRAM timing for each bank - Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems - Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs - Support up to 1.5 GB memory space (256Mb DRAM technology) - Flexible row and column addresses - 64-bit data width and 3.3V DRAM interface - Programmable I/O drive capability for MA, command, and MD signals - Two-bank interleaving for 16Mbit SDRAM support - Two-bank and four bank interleaving for 64Mbit SDRAM support - Supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on LRU - Independent SDRAM control for each bank - Seamless DRAM command scheduling for maximum DRAM bus utilization Features 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A OVERVIEW The KT133A chipset (VT8363A north bridge and VT82C686A south bridge) is a high performance, cost-effective and energy efficient system controller for the implementation of AGP / PCI / ISA desktop personal computer systems based on 64-bit SocketA (AMD Athlon) processors. The VT8363A supports FSB speeds of 200 and 266 MHz. Athlon Host CPU Address Out Data In SYSCLK, SYSCLK# INTR, NMI, SMI#, STPCLK#, IGNNE#, FERR#, A20M#, PWROK, INIT#, RESET# CKE 3D Graphics Controller PCLK BIOS ROM ATA 33 / 66 USB Ports 0-3 AC97 Audio Codec AC97 Link MC97 Modem Codec ISA Bus RTC Crystal Figure 1. KT133A System Block Diagram Using the VT82C686A South Bridge The VT8363A supports eight banks of DRAMs up to 1.5 GB. The DRAM controller supports standard Synchronous DRAM (SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible mix / match manner. The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 66/100/133 MHz. The six banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs. The VT8363A system controller also supports full AGP v2.0 capability for maximum bus utilization including 1x, 2x and 4x mode transfers, SBA (SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four level post-write request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for deep pipelined and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP / PCI remapping control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and Windows-98 / Windows 2000 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable multimedia accelerators. The VT8363A supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to the CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation, fortyeight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line, MemoryPreliminary Revision 0.1, October 9, 2000 -4Overview 1 The KT133A chip set consists of the VT8363A system controller (552 pin BGA) and the VT82C686A PCI to ISA bridge (352 pin BGA). The system controller provides superior performance between the CPU, DRAM, AGP bus, and PCI bus with pipelined, burst, and concurrent operation. 0 (+ & ' ' 3 0 7 6+ +4 # ' . & GCLK PROCRDY CONNECT CFWDRST KT133A Memory Bus MCLK HCLK PCLK SDRAM Clock Buffer AGP Bus GCKRUN# VT8363A PCKRUN# North Bridge 552 BGA PCI Bus SUSCLK, SUSST1# Super South CPUSTP# PCISTP# VT82C686A South Bridge 352 BGA SMBus Power Plane & Peripheral Control GPIO and ACPI Events Hardware Monitoring Inputs Keyboard / PS2 Mouse Serial Ports 1 and 2 Parallel Port Floppy Drive Interface MIDI / Game Ports Clock Generator 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are supported such as snoop ahead, snoop filtering, L1/L2 write-back forward to PCI master, and L1/L2 write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance. The 352-pin Ball Grid Array VT82C686A PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant). The VT82C686A also includes an integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 256 byte CMOS RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-33/66 for 33/66 MB/sec transfer rate, integrated USB interface with root hub and four function ports with built-in physical layer transceivers, Distributed DMA support, and OnNow / ACPI compliant advanced configuration and power management interface. The VT82C686A also includes an AC97 / MC97 link for interface to external audio and modem codecs, and all "Super-I/O" functions (serial ports, parallel port, and floppy drive interface and game port). For sophisticated power management, KT133A provides independent clock stop control for the CPU / SDRAM, PCI, and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for the SDRAM control signals for Suspend-to-DRAM operation. The VT82C686A also includes a complete hardware monitoring subsystem for monitoring and control of internal and external (motherboard and system) conditions including voltages, temperatures, fan speeds, switch open/close states, etc. Coupled with the VT82C686A south bridge chip, a complete power conscious PC main board can be implemented with no external TTLs. The KT133A chipset is ideal for high performance, high quality, high energy efficient and high integration desktop AGP / PCI / ISA computer systems. Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -5- 1 Overview 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A PINOUTS Figure 2. VT8363A KT133A Ball Diagram (Top View) Key 1 NC NC NC NC NC SCAN IN1 NC SCAN IN4 SCAN ENA SCAN OUT4 P GNT# GNT 3# REQ 1# AD29 AD24 AD20 AD16 2 GND NC NC NC NC SCAN IN0 SCAN IN3 SCAN IN5 SCAN IN7 SCAN OUT5 SCAN OUT7 REQ 4# GNT 1# AD26 AD23 AD22 AD18 3 AIN 14# AIN 12# NC NC NC NC GND SCAN OUT0 SCAN IN6 SCAN OUT6 GND GNT 4# REQ 2# AD25 GND CBE 3# AD19 DEV SEL# GND AD12 AD7 GND AD0 SBA 3 SBA 5 SBA 4 4 AIN CLK# GND PROC RDY NC NC NC NC NC DFT IN NC P REQ# REQ 3# VCC3 AD31 AD30 AD21 AD17 STOP# CBE 1# AD14 AD6 PCK RUN# AD1 SBA 7 SBA 6 GD31 5 AIN 9# AIN 13# AIN 10# CON NECT CKFD RST SCAN IN2 NC SCAN OUT2 NC NC NC GNT 0# GNT 2# AD28 AD27 FRM# CBE 2# T RDY# AD10 AD9 PCLK RE SET# VCC Q G REQ# GND GD29 6 AIN 3# AIN 2# AIN 4# VTT DIN VAL# VCC3 SCAN OUT1 VCC3 GND SCAN OUT3 VCC3 GND REQ 0# VCC3 GND I RDY# WSC# VCC3 GND GND 7 AIN 11# GND AIN 5# AIN 6# AIN 8# GND G7 H J K L M N P R T U V W Y7 8 D11# D9# D14# 9 D0# D3# D13# VTT 10 DICLK 0# GND D2# 11 D5# D4# D25# 12 D7# D6# D16# VTT 13 D18# GND D17# 14 D20# 15 D22# 16 D40# GND D41# 17 D43# D42# D34# 18 D44# DICLK 2# D45# VTT 19 D47# GND D38# 20 D56# D39# D57# 21 D59# D60# D58# VTT D61# S2K GND GND HCK GND VCC3 VCC3 GND VCC3 MD13 GND MCK VCC3 GND MA7 strap VCC3 VCC3 GND VCC3 MD58 MD26 GND MD27 MD60 22 D62# GND D52# D54# S2K COMP S2K VCC HCLK VCC HCK MD4 MD39 MD9 MD45 MD14 VCC MCK MCLK MA3 strap MA5 strap MA6 strap MA14 strap CS4# DQM 1 MD16 MD56 MD24 MD25 MD57 23 DICLK 3# D63# D55# AOUT 11# VTT CLK VREF MD1 TEST IN MD6 MD7 MD42 MD10 MD46 MCLK F DQM 2 VCC3 MA1# strap MA4 strap MA13 strap CS5# DQM 0 24 D49# D53# AOUT 4# AOUT 10# AOUT 5# AOUT 8# MD32 MD34 GND MD37 MD40 GND MD47 25 26 A B C D E F G H J K L M N P R T U V W Y D19# DOCLK 1# D21# D23# VTT 0 (+ & ' ' 3 0 7 6+ +4 # ' . & DOCLK 0# AIN 7# VTT 8 D12# D8# D15# D1# D28# D29# D30# D33# D37# D36# D48# D10# D27# D26# D31# VTT 14 DICLK DOCLK 1# 2# D32# 15 GND 16 D35# VTT 17 D51# D46# GND 9 S2K VREF 10 VTT 11 GND 12 D24# 13 D50# 18 GND 19 S2K VREF G20 H J DOCLK AOUT 3# 3# GND AOUT 2# AOUT AOUT 6# 9# AOUT AOUT CLK# 12# AOUT VTT 7# AOUT AOUT 13# 14# MD0 MD35 MD3 MD5 MD8 MD11 MD44 MD33 MD2 MD36 MD38 MD41 MD43 MD12 CKE3 SCASB# CPU VTT 13 Pins VTT 14 VCC3 VCC3 VTT K10 L VCC3 11 VCC3 12 VCC3 15 VCC3 16 VTT VTT K17 L VCC3 K L VCC3 GND GND GND GND GND GND GND VCC3 VCC3 M N P GND GND GND GND GND M N P VCC3 M N P PCI VCC3 VCC3 GND GND GND GND GND GND GND VCC3 DRAM Pins GND GND GND GND GND VCC3 Pins VCC3 R T GND GND GND GND GND GND R T VCC3 R T VCC3 VCC3 VCC Q GND 11 GND 12 GND 13 GND 14 GND 15 GND 16 VCC3 MD15 SCASA# strap DQM CKE1 7 SCASC# CKE4 GND U10 U17 VCC3 U LOCK# SERR# AD15 AD13 PAR AD11 AD8 AD5 AD3 SBA 0 GND SBS# VCC3 VCC Q VCC Q VCC3 VCC Q VCC3 VCC Q VCC3 VCC3 V AGP 13 Pins 14 W DQM 3 DQM 6 SRASC# MA0 SRASA# CKE5 strap strap SRASB# MA9 MA8 MA2 strap strap strap MA12 MA11 MA10 strap strap strap GND CS0# CS1# CS2# 1 8 9 10 11 12 15 16 17 18 19 Y20 AA CBE0# AB AC AD AE AF AD4 AD2 SBA 1 SBA 2 SBS VCC3 G GNT# ST0 VCC Q GDS1 1 GDS 1# GD26 GND ST1 GRBF# ST2 GD30 VCC Q GBE 3# G PIPE# VCC Q G FRM# G WBF# GD19 GND GI RDY# VCC Q GD17 GND GD23 GD28 GD27 GD25 GD24 GND GD21 GD18 VCC GND Q G G STOP# DSEL# GT G RDY# PAR GBE GD12 1# GBE GD14 2# GD15 GD13 VCC GCK G CLK VCC Q VCC Q GND GCK GCLK F GDS0 GND GD2 GD8 VCC QQ GND QQ VCC Q GD4 VCC Q N COMP P COMP GD1 GND VSUS 3 SUS ST# PWR OK MD62 DQM CS3# 5 CKE0 MD48 SWEA# SWEC# strap MD21 MD22 MD55 MD23 MD17 GND MD53 MD54 MD59 DQM 4 CKE2 MD49 SWEB# MD18 MD50 MD51 MD52 GD11 GND GBE 0# MD30 MD63 MD28 MD61 GDS0# GD9 GD6 GND GD5 GD0 MD19 MD20 GD22 GD20 AGP VREF GD16 GD10 GD7 GD3 MD31 MD29 Preliminary Revision 0.1, October 9, 2000 -6- Pinouts 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Table 1. VT8363A KT133A Pin List (Numerical Order) Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Y23 Y24 Y25 Y26 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 Pin Names Pin # Pin Name A01 NC D03 NC G05 NC P01 IO AD29 A02 P GND D04 NC G06 O SCANOUT1 P02 IO AD26 G21 P GNDHCK A03 O AIN14# D05 O CONNECT P03 IO AD25 D06 P VTT A04 O AINCLK# G22 I HCLK P04 IO AD31 A05 O AIN09# D07 O AIN06# G23 IO MD01 P05 IO AD28 P06 P VCC3 A06 O AIN03# D08 I DOCLK0# G24 IO MD32 D09 P VTT P21 P GNDMCK A07 O AIN11# G25 IO MD00 P22 P VCCMCK A08 IO D11# D10 IO D12# G26 IO MD33 A09 IO D00# D11 IO D15# H01 I SCANIN4 P23 I MCLKF D12 P VTT A10 O DICLK0# H02 I SCANIN5 P24 IO MD15 A11 IO D05# D13 IO D28# H03 O SCANOUT0 P25 O SCASA# / strap A12 IO D07# D14 IO D29# H04 NC P26 O CKE3 / SCASB# D15 P VTT A13 IO D18# H05 O SCANOUT2 R01 IO AD24 H06 P VCC3 A14 IO D20# D16 IO D30# R02 IO AD23 H21 P GND R03 P GND A15 IO D22# D17 IO D33# D18 P VTT H22 P VCCHCK A16 IO D40# R04 IO AD30 A17 IO D43# D19 IO D37# H23 I TESTIN R05 IO AD27 R06 P GND A18 IO D44# D20 IO D36# H24 IO MD34 D21 P VTT R21 P VCC3 A19 IO D47# H25 IO MD35 A20 IO D56# D22 IO D54# H26 IO MD02 R22 O MCLK A21 IO D59# D23 I AOUT11# J01 I SCANENA R23 O DQM2 / CAS2# A22 IO D62# D24 I AOUT10# J02 I SCANIN7 R24 O DQM7 / CAS7# A23 O DICLK3# D25 I AOUTCLK# J03 I SCANIN6 R25 O CKE1 / SCASC# A24 IO D49# D26 I AOUT12# J04 I DFTIN R26 O DQM3 / CAS3# A25 I DOCLK3# E01 NC J05 NC T01 IO AD20 J06 P GND A26 I AOUT03# E02 NC T02 IO AD22 J21 P VCC3 E03 NC T03 IO CBE3# B01 NC E04 NC B02 NC J22 IO MD04 T04 IO AD21 B03 O AIN12# E05 O CFWDRST J23 IO MD06 T05 IO FRAME# B04 P GND J24 P GND E06 O DINVAL# T06 IO IRDY# T21 P GND B05 O AIN13# E07 O AIN08# J25 IO MD03 B06 O AIN02# E08 O AIN07# J26 IO MD36 T22 O MA03 / strap B07 P GND T23 P VCC3 E09 IO D10# K01 O SCANOUT4 T24 P GND B08 IO D09# E10 IO D08# K02 O SCANOUT5 B09 IO D03# E11 IO D01# K03 O SCANOUT6 T25 O CKE4 / SRASC# B10 P GND E12 IO D27# K04 NC T26 O DQM6 / CAS6# B11 IO D04# E13 IO D26# K05 NC U01 IO AD16 B12 IO D06# E14 IO D31# K06 O SCANOUT3 U02 IO AD18 B13 P GND K21 P VCC3 E15 O DICLK1# U03 IO AD19 B14 IO D19# E16 I DOCLK2# K22 IO MD39 U04 IO AD17 B15 I DOCLK1# E17 IO D35# K23 IO MD07 U05 IO CBE2# B16 P GND E18 IO D51# K24 IO MD37 U06 O WSC# B17 IO D42# E19 IO D46# K25 IO MD05 U21 O MA07 / strap B18 O DICLK2# E20 IO D48# K26 IO MD38 U22 O MA05 / strap B19 P GND E21 IO D61# L01 O PGNT# U23 O MA01# / strap B20 IO D39# E22 I S2KCOMP L02 O SCANOUT7 U24 O MA00 / strap E23 P VTT L03 P GND B21 IO D60# U25 O SRASA# / strap B22 P GND E24 I AOUT05# L04 I PREQ# U26 O CKE5 / SRASB# E25 P VTT B23 IO D63# L05 NC V01 IO LOCK# L06 P VCC3 B24 IO D53 # E26 I AOUT07# V02 IO SERR# B25 P GND L21 P GND F01 I SCANIN1 V03 IO DEVSEL# B26 I AOUT02# F02 I SCANIN0 L22 IO MD09 V04 IO STOP# C01 NC F03 NC L23 IO MD42 V05 IO TRDY# V06 P VCC3 C02 NC F04 NC L24 IO MD40 C03 NC V21 P VCC3 F05 I SCANIN2 L25 IO MD08 F06 P VCC3 C04 I PROCRDY L26 IO MD41 V22 O MA06 / strap F07 P GND M01 O GNT3# V23 O MA04 / strap C05 O AIN10# F08 P VTT C06 O AIN04# M02 I REQ4# V24 O MA09 / strap F09 P GND C07 O AIN05# M03 O GNT4# V25 O MA08 / strap F10 P S2KVREF C08 IO D14# M04 I REQ3# V26 O MA02 / strap F11 P VTT C09 IO D13# M05 O GNT0# W01 IO AD15 F12 P GND M06 P GND C10 IO D02# W02 IO PAR W03 P GND M21 P VCC3 C11 IO D25# F13 IO D24# F14 P VTT C12 IO D16# M22 IO MD45 W04 IO CBE1# C13 IO D17# F15 IO D32# M23 IO MD10 W05 IO AD10 F16 P GND M24 P GND W06 P GND C14 IO D21# F17 P VTT W21 P VCC3 C15 IO D23# M25 IO MD11 C16 IO D41# F18 IO D50# M26 IO MD43 W22 O MA14 / strap F19 P GND N01 I REQ1# C17 IO D34# W23 O MA13 / strap F20 P S2KVREF C18 IO D45# N02 O GNT1# W24 O MA12 / strap F21 P S2KGND C19 IO D38# N03 I REQ2# W25 O MA11 / strap F22 P S2KVCC N04 P VCC3 C20 IO D57# W26 O MA10 / strap F23 P CLKVREF N05 O GNT2# Y01 IO AD13 C21 IO D58# C22 IO D52# F24 I AOUT08# N06 I REQ0# Y02 IO AD11 C23 IO D55# F25 I AOUT13# N21 IO MD13 Y03 IO AD12 C24 I AOUT04# F26 I AOUT14# N22 IO MD14 Y04 IO AD14 C25 I AOUT06# G01 NC N23 IO MD46 Y05 IO AD09 Y06 P GND C26 I AOUT09# G02 I SCANIN3 N24 IO MD47 D01 NC G03 P GND Y21 P GND N25 IO MD44 D02 NC G04 NC N26 IO MD12 Y22 O CS4# / RAS4# Center VCC25 Pins (26 pins): J9,11-12,15-16, K9,18, L9,18, M9,18, N9,18, P9,18, R9,18, T9,18, U9,18, V10,13,15,17-18 Center GND Pins (36 pins): L11-16, M11-16, N11-16, P11-16, R11-16, T11-16 O CS5# / RAS5# AC25 IO MD49 P GND AC26 O CKE2 / SWEB# O CS0# / RAS0# AD01 I SBA1 O CS1# / RAS1# AD02 I SBA0 IO CBE0# AD03 I SBA3 IO AD08 AD04 I SBA7 IO AD07 AD05 I GREQ# IO AD06 AD06 IO GD30 I PCLK AD07 IO GD26 P VCC3 AD08 IO GBE3# P VCCQ AD09 IO GD23 P GND AD10 IO GD19 I GRBF# AD11 IO GD17 P VCCQ AD12 IO GBE1# P GND AD13 IO GD12 P VCCQ AD14 IO GD11 P GND AD15 IO GDS0 P VCCGCK AD16 IO GBE0# P VCCQ AD17 IO GD4 P GND AD18 IO GD1 P VCCQQ AD19 IO MD30 P VCCQ AD20 IO MD28 P GND AD21 P GND P VSUS3 AD22 IO MD24 P VCC3 AD23 IO MD22 O DQM1 / CAS1# AD24 P GND O DQM0 / CAS0# AD25 IO MD18 O DQM5 / CAS5# AD26 IO MD50 O CS3# / RAS3# AE01 I SBA2 AE02 P GND O CS2# / RAS2# IO AD04 AE03 I SBA5 IO AD05 AE04 I SBA6 P GND AE05 P GND IO PCKRUN# AE06 IO GD28 I RESET# AE07 IO GD25 AE08 P GND O GGNT# IO GDS1 AE09 IO GD21 O ST1 AE10 IO GD18 AE11 P GND O ST2 IO GFRM# AE12 IO GBE2# IO GIRDY# AE13 IO GD14 AE14 P GND IO GSTOP# IO GDSEL# AE15 IO GDS0# O GCLK AE16 IO GD6 P GNDGCK AE17 P GND IO GD2 AE18 IO GD0 P GNDQQ AE19 IO MD63 I NCOMP AE20 IO MD61 I SUSST# AE21 IO MD27 IO MD62 AE22 IO MD25 IO MD58 AE23 IO MD55 IO MD16 AE24 IO MD53 IO MD48 AE25 IO MD19 O SWEA# / strap AE26 IO MD51 O CKE0 / SWEC# AF01 I SBS O DQM4 / CAS4# AF02 I SBS# IO AD02 AF03 I SBA4 IO AD03 AF04 IO GD31 IO AD00 AF05 IO GD29 IO AD01 AF06 IO GD27 P VCCQ AF07 IO GD24 O ST0 AF08 IO GD22 IO GDS1# AF09 IO GD20 AF10 P AGPVREF P VCCQ I GPIPE# AF11 IO GD16 I GWBF# AF12 IO GD15 P VCCQ AF13 IO GD13 IO GTRDY# AF14 IO GD10 IO GPAR / AF15 IO GD9 P VCCQ AF16 IO GD7 I GCLKF AF17 IO GD5 IO GD8 AF18 IO GD3 P VCCQ AF19 IO MD31 I PCOMP AF20 IO MD29 I PWROK AF21 IO MD60 IO MD59 AF22 IO MD57 IO MD26 AF23 IO MD23 IO MD56 AF24 IO MD54 IO MD21 AF25 IO MD20 IO MD17 AF26 IO MD52 Center VCCQ Pins (5 pins): V9,11-12,14,16 Center VTT Pins (5 pins): J10, 13-14, 17-18 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -7- 1 Preliminary Revision 0.1, October 9, 2000 Pinouts 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Table 2. VT8363A KT133A Pin List (Alphabetical Order) Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # AC21 AE21 AD20 AF20 AD19 AF19 G24 G26 H24 H25 J26 K24 K26 K22 L24 L26 L23 M26 N25 M22 N23 N24 AB23 AC25 AD26 AE26 AF26 AE24 AF24 AE23 AC22 AF22 AB21 AC20 AF21 AE20 AB20 AE19 A01 B01 B02 C01 C02 C03 D01 D04 E01 E02 E03 E04 F03 F04 G01 G04 G05 H04 J05 K04 L05 AB18 W02 AB04 AA05 AC18 L01 L04 C04 AC19 N06 N01 N03 M04 M02 AB05 E22 F21 F22 F10 F20 AD02 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Pin Names Pin # Pin Name AC03 IO AD00 A09 IO D00# AA24 O DQM5 / CAS5# Y24 P GND AC04 IO AD01 E11 IO D01# T26 O DQM6 / CAS6# AA08 P GND AC01 IO AD02 C10 IO D02# R24 O DQM7 / CAS7# AA11 P GND AC02 IO AD03 B09 IO D03# T05 IO FRAME# AA13 P GND AB01 IO AD04 B11 IO D04# AD16 IO GBE0# AA16 P GND AB02 IO AD05 A11 IO D05# AD12 IO GBE1# AA19 P GND AA04 IO AD06 B12 IO D06# AE12 IO GBE2# AB03 P GND AA03 IO AD07 A12 IO D07# AD08 IO GBE3# AD21 P GND AA02 IO AD08 E10 IO D08# AB14 O GCLK AD24 P GND Y05 IO AD09 B08 IO D09# AC15 I GCLKF AE02 P GND W05 IO AD10 E09 IO D10# AE18 IO GD0 AE05 P GND Y02 IO AD11 A08 IO D11# AD18 IO GD1 AE08 P GND Y03 IO AD12 D10 IO D12# AB16 IO GD2 AE11 P GND Y01 IO AD13 C09 IO D13# AF18 IO GD3 AE14 P GND Y04 IO AD14 C08 IO D14# AD17 IO GD4 AE17 P GND W01 IO AD15 D11 IO D15# AF17 IO GD5 AB15 P GNDGCK U01 IO AD16 C12 IO D16# AE16 IO GD6 G21 P GNDHCK U04 IO AD17 C13 IO D17# AF16 IO GD7 P21 P GNDMCK U02 IO AD18 A13 IO D18# AC16 IO GD8 D02 P GNDPLL1 U03 IO AD19 B14 IO D19# AF15 IO GD9 D03 P GNDPLL2 T01 IO AD20 A14 IO D20# AF14 IO GD10 AB17 P GNDQQ T04 IO AD21 C14 IO D21# AD14 IO GD11 M05 O GNT0# T02 IO AD22 A15 IO D22# AD13 IO GD12 N02 O GNT1# R02 IO AD23 C15 IO D23# AF13 IO GD13 N05 O GNT2# R01 IO AD24 F13 IO D24# AE13 IO GD14 M01 O GNT3# P03 IO AD25 C11 IO D25# AF12 IO GD15 M03 O GNT4# P02 IO AD26 E13 IO D26# AF11 IO GD16 AC13 IO GPAR / GCKRUN# R05 IO AD27 E12 IO D27# AD11 IO GD17 AC09 I GPIPE# P05 IO AD28 D13 IO D28# AE10 IO GD18 K05 O GPOUT P01 IO AD29 D14 IO D29# AD10 IO GD19 AA09 I GRBF# R04 IO AD30 D16 IO D30# AF09 IO GD20 AD05 I GREQ# P04 IO AD31 E14 IO D31# AE09 IO GD21 AB12 IO GSTOP# F15 IO D32# AF08 IO GD22 AC12 IO GTRDY# AF10 P AGPVREF B06 O AIN02# D17 IO D33# AD09 IO GD23 AC10 I GWBF# A06 O AIN03# C17 IO D34# AF07 IO GD24 G22 I HCLK C06 O AIN04# E17 IO D35# AE07 IO GD25 T06 IO IRDY# C07 O AIN05# D20 IO D36# AD07 IO GD26 V01 IO LOCK# D07 O AIN06# D19 IO D37# AF06 IO GD27 U24 O MA00 / strap E08 O AIN07# C19 IO D38# AE06 IO GD28 U23 O MA01# / strap E07 O AIN08# B20 IO D39# AF05 IO GD29 V26 O MA02 / strap A05 O AIN09# A16 IO D40# AD06 IO GD30 T22 O MA03 / strap C05 O AIN10# C16 IO D41# AF04 IO GD31 V23 O MA04 / strap A07 O AIN11# B17 IO D42# AD15 IO GDS0 U22 O MA05 / strap B03 O AIN12# A17 IO D43# AE15 IO GDS0# V22 O MA06 / strap B05 O AIN13# A18 IO D44# AB07 IO GDS1 U21 O MA07 / strap A03 O AIN14# C18 IO D45# AC07 IO GDS1# V25 O MA08 / strap A04 O AINCLK# E19 IO D46# AB13 IO GDSEL# V24 O MA09 / strap B26 I AOUT02# A19 IO D47# AB10 IO GFRM# W26 O MA10 / strap A26 I AOUT03# E20 IO D48# AB06 O GGNT# W25 O MA11 / strap C24 I AOUT04# A24 IO D49# AB11 IO GIRDY# W24 O MA12 / strap E24 I AOUT05# F18 IO D50# W23 O MA13 / strap A02 P GND C25 I AOUT06# E18 IO D51# W22 O MA14 / strap B04 P GND E26 I AOUT07# C22 IO D52# P23 I MCLKF B07 P GND F24 I AOUT08# B24 IO D53 # R22 O MCLK B10 P GND C26 I AOUT09# D22 IO D54# G25 IO MD00 B13 P GND D24 I AOUT10# C23 IO D55# G23 IO MD01 B16 P GND D23 I AOUT11# A20 IO D56# H26 IO MD02 B19 P GND D26 I AOUT12# C20 IO D57# J25 IO MD03 B22 P GND F25 I AOUT13# C21 IO D58# J22 IO MD04 B25 P GND F26 I AOUT14# A21 IO D59# K25 IO MD05 F07 P GND D25 I AOUTCLK# B21 IO D60# J23 IO MD06 F09 P GND AA01 IO CBE0# E21 IO D61# K23 IO MD07 F12 P GND W04 IO CBE1# A22 IO D62# L25 IO MD08 F16 P GND U05 IO CBE2# B23 IO D63# L22 IO MD09 F19 P GND T03 IO CBE3# V03 IO DEVSEL# M23 IO MD10 G03 P GND E05 O CFWDRST J04 I DFTIN M25 IO MD11 H21 P GND AB25 O CKE0 / SWEC# A10 O DICLK0# N26 IO MD12 J06 P GND R25 O CKE1 / SCASC# E15 O DICLK1# N21 IO MD13 J24 P GND AC26 O CKE2 / SWEB# B18 O DICLK2# N22 IO MD14 L03 P GND P26 O CKE3 / SCASB# A23 O DICLK3# P24 IO MD15 L21 P GND T25 O CKE4 / SRASC# E06 O DINVAL# AB22 IO MD16 M06 P GND U26 O CKE5 / SRASB# D08 I DOCLK0# AC24 IO MD17 M24 P GND B15 I DOCLK1# AD25 IO MD18 F23 P CLKVREF R03 P GND D05 O CONNECT E16 I DOCLK2# AE25 IO MD19 R06 P GND Y25 O CS0# / RAS0# A25 I DOCLK3# AF25 IO MD20 T21 P GND Y26 O CS1# / RAS1# AA23 O DQM0 / CAS0# AC23 IO MD21 T24 P GND AA26 O CS2# / RAS2# AA22 O DQM1 / CAS1# W03 P GND AD23 IO MD22 AA25 O CS3# / RAS3# R23 O DQM2 / CAS2# W06 P GND AF23 IO MD23 Y22 O CS4# / RAS4# R26 O DQM3 / CAS3# AD22 IO MD24 Y06 P GND Y23 O CS5# / RAS5# AB26 O DQM4 / CAS4# AE22 IO MD25 Y21 P GND Center VCC25 Pins (26 pins): J9,11-12,15-16, K9,18, L9,18, M9,18, N9,18, P9,18, R9,18, T9,18, U9,18, V10,13,15,17-18 Center GND Pins (36 pins): L11-16, M11-16, N11-16, P11-16, R11-16, T11-16 MD26 AD01 I SBA1 MD27 AE01 I SBA2 MD28 AD03 I SBA3 MD29 AF03 I SBA4 MD30 AE03 I SBA5 MD31 AE04 I SBA6 MD32 AD04 I SBA7 MD33 AF01 I SBS MD34 AF02 I SBS# MD35 J01 I SCANENA MD36 F02 I SCANIN0 MD37 F01 I SCANIN1 MD38 F05 I SCANIN2 MD39 G02 I SCANIN3 MD40 H01 I SCANIN4 MD41 H02 I SCANIN5 MD42 J03 I SCANIN6 MD43 J02 I SCANIN7 MD44 H03 O SCANOUT0 MD45 G06 O SCANOUT1 MD46 H05 O SCANOUT2 MD47 K06 O SCANOUT3 MD48 K01 O SCANOUT4 MD49 K02 O SCANOUT5 MD50 K03 O SCANOUT6 MD51 L02 O SCANOUT7 MD52 P25 O SCASA#/strap MD53 V02 IO SERR# MD54 U25 O SRASA#/strap MD55 AC06 O ST0 MD56 AB08 O ST1 MD57 AB09 O ST2 MD58 V04 IO STOP# MD59 AB19 I SUSST# MD60 AB24 O SWEA#/strap MD61 H23 I TESTIN MD62 V05 IO TRDY# MD63 F06 P VCC3 NC H06 P VCC3 NC J21 P VCC3 NC K21 P VCC3 NC L06 P VCC3 NC M21 P VCC3 NC N04 P VCC3 NC P06 P VCC3 NC R21 P VCC3 NC T23 P VCC3 NC V06 P VCC3 NC V21 P VCC3 NC W21 P VCC3 NC AA06 P VCC3 NC AA21 P VCC3 NC AA14 P VCCGCK NC H22 P VCCHCK NC P22 P VCCMCK NC AA07 P VCCQ NC AA10 P VCCQ NC AA12 P VCCQ NC AA15 P VCCQ I NCOMP AA18 P VCCQ IO PAR AC05 P VCCQ IO PCKRUN# AC08 P VCCQ I PCLK AC11 P VCCQ I PCOMP AC14 P VCCQ O PGNT# AC17 P VCCQ I PREQ# AA17 P VCCQQ I PROCRDY AA20 P VSUS3 I PWROK D06 P VTT I REQ0# D09 P VTT I REQ1# D12 P VTT I REQ2# D15 P VTT I REQ3# D18 P VTT I REQ4# D21 P VTT I RESET# E23 P VTT I S2KCOMP E25 P VTT P S2KGND F08 P VTT P S2KVCC F11 P VTT P S2KVREF F14 P VTT P S2KVREF F17 P VTT I SBA0 U06 O WSC# Center VCCQ Pins (5 pins): V9,11-12,14,16 Center VTT Pins (5 pins): J10, 13-14, 17-18 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -8- 1 Pinouts 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A PIN DESCRIPTIONS Table 3. VT8363A KT133A Pin Descriptions CPU Interface Signal Name CFWDRST CONNECT PROCRDY AIN[14-2]# Pin # E5 D5 C4 (see pin list) I/O O O I O Signal Description CLK Forward Reset. Reset the CLK forward circuitry for the AthlonTM interface. Connect. Used for power management and CLK-forward initialization at reset. Processor Ready. Used for power management and CLK-forward initialization at reset. Host CPU Address / Command Output. Unidirectional system address / command interface to the processor from the system controller. It is used to transfer probes or data movement commands into the processor during PCI-to-DRAM cycles to snoop the CPU internal Cache. AIN[14:2]# is skew-aligned with the forward clock, AINCLK# Host CPU Address Output Clock. Single-ended forwarded clock for the AIN[14:2]# bus that is driven by the system controller. Both rising and falling edges are used to transfer addresses or commands to the processor. Host CPU Address Input. Unidirectional system address / command interface from the processor to the system controller. It is used to transfer processor commands or probes responses to the system controller. AOUT[14:2]# is skew-aligned with the forward clock, AOUTCLK# Host CPU Address Input Clock. Single-ended forwarded clock for the AOUT[14:2]# bus that is driven by the processor. Both rising and falling edges are used to transfer commands or probe responses. Host CPU Data. Bi-directional interface between the processor and the system controller for data movement. D[63:0]# bus is skew-aligned with either the DICLK[3:0]# or DOCLK[3:0]# forward clocks. Host CPU Data Input Clock. Single-ended forwarded clocks for the D[63:0]# bus, driven by the system controller to the processor. Each 16-bit data word is skew-aligned with one of these clocks. Both rising and falling edges are used to transfer data to the pocessor. Host CPU Data Output Clock. Single-ended forwarded clocks for the D[63:0]# bus, driven by the processor to the system controller. Each 16-bit data word is skew-aligned with one of these clocks. Both rising and falling edges are used to transfer data to the system controller. Host CPU Data Read In Valid. Driven by the system controller to control the flow of data into the processor. DINVAL# can be used to introduce an arbitrary number of cycles between octawords into the processor. AINCLK# A4 AOUT[14-2]# (see pin list) AOUTCLK# D25 D[63-0]# (see pin list) DICLK[3-0]# A23, B18, E15, A10 DOCLK[3-0]# A25, E16, B15, D8 DINVAL# E6 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & O I I IO O I O -9- 1 Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout shown) as a guide for PCB component placement. Other PCB layouts (AT, LPX, and NLX) were also considered and can typically follow the same general component placement. Up to Five PCI Slots AGP Slot 1 Socket-462 Athlon CPU Power Supply 26 A VT8231 South Bridge IDE Connectors Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & CPU nc nc VT PCI 8363 AGP ... DRAM AF 1, 2, or 3 DRAM Modules 1 -10- Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A DRAM Interface Signal Name MD[63:0] MA14 / strap, MA13 / strap, MA12 / strap, MA11 / strap, MA10 / strap, MA9 / strap, MA8 / strap, MA7 / strap, MA6 / strap, MA5 / strap, MA4 / strap, MA3 / strap, MA2 / strap, MA1 / strap, MA0 / strap Pin # (see pinout tables) W22 W23 W24 W25 W26 V24 V25 U21 V22 U22 V23 T22 V26 U23 U24 I/O IO O/I Signal Description Memory Data. These signals are connected to the DRAM data bus. Memory Address. DRAM address lines Strap MA14 MA13-12 MA11 MA10-9 MA8-4 MA3-0 Register Rx68[0] RxB4[5-4] RxB6[7] RxB4[1-0] RxB6[4-0] RxB3[7-4] Description CPU Clock Frequency Internal Pullup Strength S2K Edge/Central DQ Output Drive Strength S2K Strobe Delay CPU Clock Divide Settings 0=100, 1=66 11=Auto, ~11=Strap 1=Edge 0=Auto, ~0=Strap 0=Auto, ~0=Strap 0=11, 1=11.5, 2=12, 3=12.5, 4=5, 5=5.5, 6=6,7=6.5,8=7,9=7.5, 10=8, 11=8.5, 12=9, 13=9.5,14=10,15=10.5 S2K Slew Rate Control 1=Disable Fast Command 1=Enable CPU Edge/Center DQ 1=Center CS[5:0]# DQM[7:0] SRASA# / strap SCASA# / strap SWEA# / strap CKE0 / SWEC#, CKE1 / SCASC#, CKE2 / SWEB#, CKE3 / SCASB#, CKE4 / SRASC#, CKE5 / SRASB# Y23, Y22, AA25, AA26, Y26, Y25 R24, T26, AA24, AB26, R26, R23, AA22, AA23 U25 P25 AB24 AB25 R25 AC26 P26 T25 U26 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & SRASA# RxB2[5] SCASA# RxB3[1] SWEA# RxB6[5] O O Data Mask. Data mask of each byte lane O O O O -11- Strap option default values are all 0 (internally pulled down) Chip Select. Chip select of each bank. Row Address Command Indicator. (see Device 0 RxB2[5]) Column Address Command Indicator. (see Device 0 RxB3[1]) Write Enable Command Indicator. (see Device 0 RxB6[5]) Clock Enables. Clock enables for each DRAM bank for powering down the SDRAM or clock control for reducing power usage and for reducing heat / temperature in high-speed memory systems. 1 Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A PCI Bus Interface Signal Name AD[31:0] Pin # (see pinout tables) T3, U5, W4, AA1 I/O IO Signal Description Address/Data Bus. The standard PCI address and data lines. The address is driven with FRAME# assertion and data is driven or received in following cycles. Command/Byte Enable. Commands are driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks. Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. Initiator Ready. Asserted when the initiator is ready for data transfer. Target Ready. Asserted when the target is ready for data transfer. Stop. Asserted by the target to request the master to stop the current transaction. Device Select. This signal is driven by the VT8363A when a PCI initiator is attempting to access main memory. It is an input when the VT8363A is acting as a PCI initiator. Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]. System Error. The VT8363A will pulse this signal when it detects a system error condition. Lock. Used to establish, maintain, and release resource lock. South Bridge Request. This signal comes from the South Bridge. PREQ# is the South Bridge request for the PCI bus. South Bridge Grant. This signal driven by the VT8363A to grant PCI access to the South Bridge. PCI Master Request. PCI master requests for PCI. PCI Master Grant. Permission is given to the master to use PCI. PCI Clock. From external clock generator. PCI Clock Run. May be used to stop PCI clock. Write Snoop Complete. Sideband PCI signal (used on the planar only in multiprocessor configurations) asserted to indicate that all snoop activity on the CPU bus initiated by the last PCI-to-DRAM write is complete and that it is safe to send an APIC interrupt message. Basically this signal is always active except when PCI master write data is not flushed. CBE[3:0]# IO FRAME# IRDY# TRDY# STOP# DEVSEL# T5 T6 V5 V4 V3 IO IO IO IO IO PAR SERR# LOCK# PREQ# PGNT# REQ[4:0]# GNT[4:0]# PCLK PCKRUN# WSC# W2 V2 V1 L4 L1 M2, M4, N3, N1, N6 M3, M1, N5, N2, M5 AA5 AB4 U6 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & IO IO IO I O I O I IO O -12- 1 Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A AGP Bus Interface Signal Name GD[31:0] Pin # (see pinout tables) AD15 I/O IO Signal Description Address/Data Bus. The standard AGP/PCI address and data lines. The address is driven with GDS0# and GDS1# assertion for AGP transfers and is driven with GFRM# assertion for PCI transfers. IO Bus Strobe 0 (AGP transactions only). Provides timing for 2x data transfer mode on GDS0 AD[15:0]. The agent that is providing the data drives this signal. AE15 IO Bus Strobe 0 complement and Bus Strobe 0 (AGP transactions only). Provides timing for GDS0# 4x data transfer mode on AD[15:0]. The agent that is providing the data drives this signal. AB7 IO Bus Strobe 1 (AGP transactions only). Provides timing for 2x data transfer mode on GDS1 AD[31:16]. The agent that is providing the data drives this signal. AC7 IO Bus Strobe 1 complement and Bus Strobe 1 (AGP transactions only). Provides timing for GDS1# 4x data transfer mode on AD[31:16]. The agent that is providing the data drives this signal. IO Command/Byte Enable. AD8, GBE[3:0]# AE12, AGP: These pins provide command information (different commands than for PCI) driven by the master (graphics controller) when requests are being enqueued using PIPE#. These AD12, pins provide valid byte information during AGP write transactions and are driven by the AD16 master. The target (this chip) drives these lines to "0000" during the return of AGP read data, but the state of these pins is ignored by the AGP master. PCI: Commands are driven with GFRM# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks. AB10 IO Frame (PCI transactions only). Assertion indicates the address phase of a PCI transfer. GFRM# Negation indicates that one more data transfer is desired by the cycle initiator. AB11 IO Initiator Ready GIRDY# AGP: For write operations, the assertion of this pin indicates that the master is ready to provide all write data for the current transaction. Once this pin is asserted, the master is not allowed to insert wait states. For read operations, the assertion of this pin indicates that the master is ready to transfer a subsequent block of read data. The master is never allowed to insert a wait state during the initial block of a read transaction. However, it may insert wait states after each block transfers. PCI: Asserted when the initiator is ready for data transfer. AC12 IO Target Ready: GTRDY# AGP: Indicates that the target is ready to provide read data for the entire transaction (when the transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data when the transfer requires more than four clocks to complete. The target is allowed to insert wait states after each block transfers on both read and write transactions. PCI: Asserted when the target is ready for data transfer. AB12 IO Stop (PCI transactions only). Asserted by the target to request the master to stop the GSTOP# current transaction. AB13 IO Device Select (PCI transactions only). This signal is driven by the VT8363A when a PCI GDSEL# initiator is attempting to access main memory. It is an input when the VT8363A is acting as PCI initiator. Not used for AGP cycles. Note: Clocking of the AGP interface is performed with GCLK; see the clock pin group for descriptions of the clock pins. Note: PCB Layout Guidelines (reference from AGP specification) 1. Total motherboard trace length 10" max, trace impedance = 65 ohms 15 ohms, minimize signal crosstalk 2. Trace lengths within groups matched to within 2 inches or better Groups are: a. GDS0#, GDS0, GD15-0, GBE1-0# b. GDS1#, GDS1, GD31-16, GBE3-2# c. SBS#, SBS, SBA7-0 3. Ground isolation should be provided around GDS0#, GDS0, GDS1# and GDS1 to prevent crosstalk with GD[31:0]. Ideally ground traces should be provided adjacent to GDSn# on the same signal layer, but at a minimum wider spaces should be provided on either side (e.g., 16 mil spaces on either side of GDSn# if GDSn# signal traces are 8 mil). Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -13- 1 Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A AGP Bus Interface (continued) Signal Name GPIPE# Pin # AC9 IO I Signal Description Pipelined Request. Asserted by the master (graphics controller) to indicate that a fullwidth request is to be enqueued by the target VT8363A. The master enqueues one request each rising edge of GCLK while GPIPE# is asserted. When GPIPE# is deasserted no new requests are enqueued across the AD bus. Read Buffer Full. Indicates if the master (graphics controller) is ready to accept previously requested low priority read data. When GRBF# is asserted, the VT8363A will not return low priority read data to the master. Write Buffer Full. SideBand Address. Provides an additional bus to pass address and command information from the master (graphics controller) to the target (the VT8363A). These pins are ignored until enabled. Sideband Strobe. Provides timing for SBA[7:0] (driven by the master) Sideband Strobe complement and SBS . Provides timing for SBA[7:0] (driven by the master) when 4x timing is supported. Status (AGP only). Provides information from the arbiter to a master to indicate what it may do. Only valid while GGNT# is asserted. 000 Indicates that previously requested low priority read or flush data is being returned to the master (graphics controller). 001 Indicates that previously requested high priority read data is being returned to the master. 010 Indicates that the master is to provide low priority write data for a previously enqueued write command. 011 Indicates that the master is to provide high priority write data for a previously enqueued write command. 100 Reserved. (arbiter must not issue, may be defined in the future). 101 Reserved. (arbiter must not issue, may be defined in the future). 110 Reserved. (arbiter must not issue, may be defined in the future). 111 Indicates that the master (graphics controller) has been given permission to start a bus transaction. The master may enqueue AGP requests by asserting PIPE# or start a PCI transaction by asserting GFRM#. ST[2:0] are always outputs from the VT8363A and inputs to the master. Request. Master request for AGP. Grant. Permission is given to the master to use AGP. Rx78[1]=0: AGP Parity. A single parity bit is provided over GD[31:0] and GBE[3:0]. Rx78[1]=1: AGP Clock Run. Used to stop the AGP bus clock to reduce bus power usage. AGP Clock. Generated by on-chip clock logic. AGP Clock Feedback. Connect to GCLK. GRBF# AA9 I SBS SBS# ST[2:0] AB9, AB8, AC6 GREQ# GGNT# GPAR / GCKRUN# GCLK GCLKF Note: For PCI operation on the AGP bus, the following pins are not required: - PERR# (parity and error reporting not required on transient data devices such as graphics controllers) - LOCK# (no lock requirement on AGP) - IDSEL (internally connected to AD16 on AGP-compliant masters) Note: Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via PCI bus INTA-B#. Note: The AGP bus supports only one master directly (REQ[3:0]# and GNT[3:0]# are not provided). External logic is required to implement additional master capability. Note that the arbitration mechanism on the AGP bus is different from the PCI bus. Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses) Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send addresses multiplexed on the AD lines) and the SBA port (to send addresses unmultiplexed). AGP masters implement one or the other or select one at initialization time (they are not allowed to change during runtime). Therefore only one of the two will be used and the signals associated with the other will not be used. Therefore the VT8363A has an internal pullup on GRBF# to maintain it in the de-asserted state in case it is not implemented on the master device. Preliminary Revision 0.1, October 9, 2000 1 AB14 AC15 AD5 AB6 AC13 0 (+ & ' ' 3 0 7 6+ +4 # ' . & I I O I O IO O I -14- GWBF# SBA[7:0] AC10 AD4, AE4, AE3, AF3, AD3, AE1, AD1, AD2 AF1 AF2 I I Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Test Functions Signal Name TESTIN Pin # H23 I/O I Signal Description PLL Test Input. Normally connected to VCC3. Clock / Reset Control Signal Name HCLK Pin # G22 I/O I Signal Description Host Clock. This pin receives the host CPU clock (66 / 100 / 133 MHz). This clock is used by all VT8363A logic that is in the host CPU domain. The memory interface logic will also use this clock if selected (memory system timing can alternately be selected to use the AGP bus clock). The CPU clock must lead the AGP clock by 0.2 0.5 nsec. PCI Clock. This pin receives a buffered host clock divided-by-6 to create 33 MHz. This clock is used by all of the VT8363A logic that is in the PCI clock domain. This clock input must be 33 MHz maximum to comply with PCI specification requirements and must be synchronous with the host CPU clock, HCLK. The host CPU clock must lead the PCI clock by 1.5 0.5 nsec. AGP Clock. This pin drives the AGP bus clock (66 MHz). This clock is used by all VT8363A logic that is in the AGP clock domain. The AGP clock is synchronous to the 200 MHz host CPU clock. AGP Clock Feedback. Connect to GCLK. DRAM Clock. Output from internal clock generator to the external clock buffer. DRAM Clock Feedback. Input from MCLK via the external clock buffer. Reset. Input from south bridge chip. When asserted, this signal resets the VT8363A and sets all register bits to the default value. The rising edge of this signal is used to sample all power-up strap options Power OK. Suspend Status. For implementation of the Suspend-to-DRAM feature. Connect to an external pullup to disable. Clock Generator PCLK AA5 GCLK AB14 GCLKF MCLK MCLKF RESET# AC15 R22 P23 AB5 PWROK SUSST# AC19 AB19 1 PCI Slots AGP Slot Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & I O I O I I I I PCLK HCLK Athlon CPU GCLKF MCLKF GCLKO VT8363A North Bridge MCLKO "Zero Delay" Clock Buffer To SDRAMs Figure 3. CPU / SDRAM / AGP / PCI Clock Connections -15- Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Power, Ground, and Test Signal Name VCC3 VSUS3 VTT Pin # (see pin list) AA20 D6, D9, D12, D15, D18, D21, E23, E25, F8, F11, F14, F17, J10, J13, J14, J17, J18 (see pin list) F10, F20 E22 F22 F21 F23 H22 G21 P22 P21 AA14 AB15 V9, V11, V12, V14, V16, AA7, AA10, AA12, AA15, AA18, AC5, AC8, AC11, AC14, AC17 AA17 AB17 AF10 I/O P P P Signal Description Power for Internal Logic and I/O Interface Logic (3.3V 5%). Suspend Power (3.3V 5%). CPU Interface Termination Voltage (x.xV 0.xV). VCCQQ GNDQQ AGPVREF 1 NCOMP PCOMP DFTIN SCANENA SCANIN[7-0] SCANOUT[7-0] AB18 AC18 J4 J1 J2, J3, H2, H1, G2, F5, F1, F2 L2, K3-K1, K6, H5, G6, H3 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & AGP 1.5V Power. P P P I I I I I O Scan Out. -16- GND S2KVREF S2KCOMP S2KVCC S2KGND CLKVREF VCCHCK GNDHCK VCCMCK GNDMCK VCCGCK GNDGCK VCCQ P P I P P P P P P P P P P Ground S2K Voltage Reference. S2K Compensation. S2K Power. S2K Ground. Clock Voltage Reference. Host CPU Clock Power (3.3V 5%). For Host CPU clock logic. Host CPU Clock Ground. Connect to main ground plane. DRAM Clock Power (3.3V 5%). For DRAM clock deskew logic. DRAM Clock Ground. Connect to main ground plane. AGP Clock Power (3.3V 5%). For AGP clock deskew logic AGP Clock Ground. Connect to main ground plane. AGP Quiet Power. AGP Quiet Ground. AGP Voltage Reference. 0.39 VCC3 to 0.41 VCC3. Typical value is 1.32V (0.40 times 3.3V). This can be provided with a resistive divider on VCC3 using 270 ohm and 180 ohm (2%) resistors. AGP N Compensation. Connect to VCCQ through a 60 ohm resistor. AGP P Compensation. Connect to GND through a 60 ohm resistor. DFT In. Scan Enable. Scan In. Pin Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A REGISTERS Register Overview The following tables summarize the configuration and I/O registers of the VT8363A. These tables also document the power-on default value ("Default") and access type ("Acc") for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), "--" for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1's to Clear individual bits). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions following these tables for details). All offset and default values are shown in hexadecimal unless otherwise indicated. Table 4. VT8363A Registers VT8363A I/O Ports Port # 22 CFB-8 CFF-C I/O Port PCI / AGP Arbiter Disable Configuration Address Configuration Data Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & Default 00 0000 0000 0000 0000 Acc RW RW RW -17Register Descriptions 1 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A VT8363A Device 0 Registers - Host Bridge Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 13-10 14-2B 2D-2C 2F-2E 30-33 37-34 38-3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Program Interface Sub Class Code Base Class Code -reservedLatency Timer Header Type Built In Self Test (BIST) Graphics Aperture Base -reservedSubsystem Vendor ID Subsystem ID -reservedCapability Pointer -reservedDefault 1106 0305 0006 0210 8n 00 00 06 00 00 00 00 0000 0008 00 0000 0000 00 0000 00A0 00 Acc RO RO RW WC RO RO RO RO -- RW RO RO RW -- W1 W1 -- RO -- Device-Specific Registers (continued) Offset 56-57 59-58 5F-5A 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E-6F DRAM Control -reservedMA Map Type DRAM Row Ending Address: Bank 0 Ending (HA[31:24]) Bank 1 Ending (HA[31:24]) Bank 2 Ending (HA[31:24]) Bank 3 Ending (HA[31:24]) Bank 4 Ending (HA[31:24]) Bank 5 Ending (HA[31:24]) DRAM Type ROM Shadow Control C0000-CFFFF ROM Shadow Control D0000-DFFFF ROM Shadow Control E0000-FFFFF DRAM Timing for Banks 0,1 DRAM Timing for Banks 2,3 DRAM Timing for Banks 4,5 -reservedDRAM Control DRAM Clock Select DRAM Refresh Counter DRAM Arbitration Control SDRAM Control DRAM Control Drive Strength -reservedPCI Bus Control PCI Buffer Control CPU to PCI Flow Control 1 CPU to PCI Flow Control 2 PCI Master Control 1 PCI Master Control 2 PCI Arbitration 1 PCI Arbitration 2 Chip Test (do not program) PMU Control PMU Control Miscellaneous Control PCI Master Access Control -reservedPLL Test Mode (do not program) Default 00 0040 01 01 01 01 01 01 00 00 00 00 EC EC EC 00 00 00 00 01 00 00 00 Default 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Acc -- RW RW RW RW RW RW RW RW RW RW RW RW RW RW -- RW RW RW RW RW RW -- Acc RW RW RW RW RW RW RW RW RW RW RW RW -- RW Device-Specific Registers Offset 50 51 52 53 54 55 Host CPU Protocol Control S2K Timing Control I S2K Timing Control II S2K Timing Control III BIU Arbitration Control BIU Control Debug (Do Not Program) Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & Default 00 00 70 00 00 Acc RW RW RW RW RW -- Offset 70 71 72 73 74 75 76 77 78 79 7A 7B 7C-7D 7E-7F -18- 1 Register Summary Tables 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Device-Specific Registers (continued) Offset C0 C1 C2 C3 C4 C5 C6 C7 C8-DF E0 E1-EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9-FB FC FD FF-FE Power Management & MiscControl Default Power Management Capability ID 01 Power Management New Pointer 00 Power Management Capabilities I 02 Power Management Capabilities II 00 Power Management Control / Status 00 Power Management Status 00 PCI-to-PCI Bridge Support Extension 00 Power Management Data 00 -reserved00 Miscellaneous Control 00 -reserved00 BIOS Scratch Register 0 00 BIOS Scratch Register 1 00 BIOS Scratch Register 2 00 BIOS Scratch Register 3 00 BIOS Scratch Register 4 00 BIOS Scratch Register 5 00 Revision ID Backdoor 00 Foundry ID FoundryID DRAM Arbitration Timer 00 -reserved0000 Back-Door Control 1 00 Back-Door Control 2 00 Back-Door Device ID 0000 Acc RO RO RO RO RW RO RO RO -- RW -- RW RW RW RW RW RW RW RW RW RW RW RW RW Device 0 Device-Specific Registers (continued) Offset 83-80 84 85-87 8B-88 8C-9F Offset A0 A1 A2 A3 A7-A4 AB-A8 AC AD AE AF B0 B1 B2 B3 Offset B3 B4 B5 B6 B7 B8 B9-BF GART/TLB Control Default Acc GART/TLB Control 0000 0000 RW Graphics Aperture Size 00 RW -reserved00 -- Gr. Aperture TLB Base Register Base 0000 0000 RW -reserved00 -- AGP Control AGP ID AGP Next Item Pointer AGP Specification Revision -reservedAGP Status AGP Command AGP Control AGP Latency Timer AGP Miscellaneous Control AGP Strobe Drive Strength AGP Pad Control / Status AGP Drive Strength AGP Pad Drive / Delay Control -reservedDefault 02 C0 20 00 1F00 0203 0000 0000 00 02 00 00 8x 63 00 00 Acc RO RO RO -- RO RW RW RW RW RW RW RW RW -- CPU Strapping/S2K Compensation Default Acc CPU Strapping Control strapping RO S2K Compensation Strapping strapping RO S2K Compensation Result 1 00 RO S2K Compensation Result 2 00 RO S2K Compensation Result 3 00 RO S2K Compensation Result 4 00 RO -reserved00 -- Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -19- 1 Register Summary Tables 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A VT8363A Device 1 - PCI-to-PCI Bridge Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-17 18 19 1A 1B 1C 1D 1F-1E 21-20 23-22 25-24 27-26 28-2B 2D-2C 2F-2E 30-33 34 35-3D 3F-3E Configuration Space Header Vendor ID Device ID Command Status Revision ID Program Interface Sub Class Code Base Class Code -reservedLatency Timer Header Type Built In Self Test (BIST) -reservedPrimary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Latency Timer I/O Base I/O Limit Secondary Status Memory Base Memory Limit (Inclusive) Prefetchable Memory Base Prefetchable Memory Limit -reservedSubsystem Vendor ID Subsystem ID -reservedCapability Pointer -reservedPCI-to-PCI Bridge Control Default 1106 8305 0007 0230 nn 00 04 06 00 00 01 00 00 00 00 00 00 F0 00 0000 FFF0 0000 FFF0 0000 00 0000 0000 00 00 00 00 Acc RO RO RW WC RO RO RO RO -- RW RO RO -- RW RW RW RO RW RW RO RW RW RW RW -- RW RW -- RO -- RW Device-Specific Registers Offset 40 41 42 43 44 45 47-46 48-7F 80 81 82 83 84 85 86 87 88-FF AGP Bus Control CPU-to-AGP Flow Control 1 CPU-to-AGP Flow Control 2 AGP Master Control AGP Master Latency Timer Back-Door Register Control Fast Write Control PCI-to-PCI Bridge Device ID -reservedCapability ID Next Pointer Power Management Capabilities 1 Power Management Capabilities 2 Power Management Control / Status Power Management Status PCI-PCI Bridge Support Extensions Power Management Data -reservedDefault 00 00 00 00 00 72 0000 00 01 00 02 00 00 00 00 00 00 Acc RW RW RW RW RW RW RW -- RO RO RO RO RW RO RO RO -- Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -20- 1 Register Summary Tables 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Configuration Space I/O All registers in the VT8363A (listed above) are addressed via the following configuration mechanism: Mechanism #1 These ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged. Port CFB-CF8 - Configuration Address......................... RW 31 Configuration Space Enable 0 Disabled................................................. default 1 Convert configuration data port writes to configuration cycles on the PCI bus ........................................always reads 0 30-24 Reserved 23-16 PCI Bus Number Used to choose a specific PCI bus in the system 15-11 Device Number Used to choose a specific device in the system (devices 0 and 1 are defined for the VT8363A) 10-8 Function Number Used to choose a specific function if the selected device supports multiple functions (only function 0 is defined for the VT8363A). 7-2 Register Number (also called the "Offset") Used to select a specific DWORD in the VT8363A configuration space ........................................always reads 0 1-0 Fixed Miscellaneous I/O One I/O port is defined in the VT8363A: Port 22. Port 22 - PCI / AGP Arbiter Disable ..............................RW ........................................ always reads 0 7-2 Reserved 1 AGP Arbiter Disable 0 Respond to GREQ# signal .....................default 1 Do not respond to GREQ# signal 0 PCI Arbiter Disable 0 Respond to all REQ# signals..................default 1 Do not respond to any REQ# signals, including PREQ# This port can be enabled for read/write access by setting bit-7 of Device 0 Configuration Register 78. Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -21- Port CFF-CFC - Configuration Data.............................. RW Refer to PCI Bus Specification Version 2.1 for further details on operation of the above configuration registers. 1 Miscellaneous and Configuration Space I/O Ports 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 7-6 - Status (0210h)............................. RWC 15 Detected Parity Error 0 No parity error detected ......................... default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ......write one to clear 14 Signaled System Error (SERR# Asserted) ........................................always reads 0 13 Signaled Master Abort 0 No abort received .................................. default 1 Transaction aborted by the master ................... ....................................write one to clear 12 Received Target Abort 0 No abort received .................................. default 1 Transaction aborted by the target...................... ....................................write one to clear 11 Signaled Target Abort........................always reads 0 0 Target Abort never signaled 10-9 DEVSEL# Timing 00 Fast 01 Medium....................................always reads 01 10 Slow 11 Reserved 8 Data Parity Error Detected 0 No data parity error detected ................. default 1 Error detected in data phase. Set only if error response enabled via command bit-6 = 1 and VT8363A was initiator of the operation in which the error occurred. .......write one to clear 7 Fast Back-to-Back Capable ...............always reads 0 6 User Definable Features.....................always reads 0 5 66MHz Capable..................................always reads 0 4 Supports New Capability list.............always reads 1 ........................................always reads 0 3-0 Reserved Device 0 Offset 8 - Revision ID (08nh) ............................. RO 7-0 Chip Revision Code .always reads 08nh (n=rev code) Device 0 Offset 9 - Programming Interface (00h) ........... RO 7-0 Interface Identifier ...........................always reads 00 Device 0 Offset A - Sub Class Code (00h) ........................ RO 7-0 Sub Class Code .......reads 00 to indicate Host Bridge Device 0 Offset B - Base Class Code (06h)....................... RO 7-0 Base Class Code .. reads 06 to indicate Bridge Device Device 0 Offset D - Latency Timer (00h) ........................ RW Specifies the latency timer value in PCI bus clocks. 7-3 2-0 Guaranteed Time Slice for CPU................default=0 Reserved (fixed granularity of 8 clks) .. always read 0 Bits 2-1 are writeable but read 0 for PCI specification compatibility. The programmed value may be read back in Offset 75 bits 5-4 (PCI Arbitration 1). Register Descriptions Device 0 Header Registers - Host Bridge All registers are located in PCI configuration space. They should be programmed using PCI configuration mechanism 1 through CF8 / CFC with bus number, function number, and device number equal to zero. Device 0 Offset 1-0 - Vendor ID (1106h) ..........................RO 15-0 ID Code (reads 1106h to identify VIA Technologies) Device 0 Offset 3-2 - Device ID (0305h)............................RO 15-0 ID Code (reads 0305h to identify the VT8363A) Device 0 Offset 5-4 -Command (0006h) ..........................RW ........................................ always reads 0 15-10 Reserved 9 Fast Back-to-Back Cycle Enable ........................ RO 0 Fast back-to-back transactions only allowed to the same agent ........................................default 1 Fast back-to-back transactions allowed to different agents 8 SERR# Enable...................................................... RO 0 SERR# driver disabled ...........................default 1 SERR# driver enabled (SERR# is used to report parity errors if bit-6 is set). 7 Address / Data Stepping ...................................... RO 0 Device never does stepping....................default 1 Device always does stepping 6 Parity Error Response........................................RW 0 Ignore parity errors & continue ..............default 1 Take normal action on detected parity errors 5 VGA Palette Snoop .............................................. RO 0 Treat palette accesses normally ..............default 1 Don't respond to palette accesses on PCI bus 4 Memory Write and Invalidate Command.......... RO 0 Bus masters must use Mem Write ..........default 1 Bus masters may generate Mem Write & Inval 3 Special Cycle Monitoring .................................... RO 0 Does not monitor special cycles .............default 1 Monitors special cycles 2 PCI Bus Master.................................................... RO 0 Never behaves as a bus master 1 Can behave as a bus master ....................default 1 Memory Space...................................................... RO 0 Does not respond to memory space 1 Responds to memory space ....................default 0 I/O Space .......................................................... RO 0 Does not respond to I/O space ...............default 1 Responds to I/O space Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -22- 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Host Bridge Header Registers (continued) Device 0 Offset E - Header Type (00h) .............................RO 7-0 Header Type Code ............reads 00: single function Device 0 Offset F - Built In Self Test (BIST) (00h) ..........RO 7 BIST Supported ......reads 0: no supported functions ........................................ always reads 0 6-0 Reserved Device 0 Offset 13-10 - Graphics Aperture Base (00000008h) .......................................................................RW 31-28 Upper Programmable Base Address Bits....... def=0 27-20 Lower Programmable Base Address Bits ...... def=0 These bits behave as if hardwired to 0 if the corresponding Graphics Aperture Size register bit (Device 0 Offset 84h) is 0. 27 26 25 24 23 22 21 20 (This Register) 76543210 (Gr Aper Size) RW RW RW RW RW RW RW RW 1M RW RW RW RW RW RW RW 0 2M RW RW RW RW RW RW 0 0 4M RW RW RW RW RW 0 0 0 8M RW RW RW RW 0 0 0 0 16M RW RW RW 0 0 0 0 0 32M RW RW 0 0 0 0 0 0 64M RW 0 0 0 0 0 0 0 128M 00000000 256M Device 0 Offset 2D-2C - Subsystem Vendor ID (0000h)R/W1 15-0 Subsystem Vendor ID............................... default = 0 This register may be written once and is then read only. Device 0 Offset 2F-2E - Subsystem ID (0000h)........... R/W1 15-0 Subsystem ID ............................................default = 0 This register may be written once and is then read only. Device 0 Offset 37-34 - Capability Pointer (000000A0h) RO Contains an offset from the start of configuration space. 31-0 AGP Capability List Pointer ........ always reads A0h ................................ always reads 00008 19-0 Reserved Note: The locations in the address range defined by this register are prefetchable. Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -23- 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 53 - BIU Arbitration Control ............... RW 7-6 Max of Contiguous Probe SysDC Before Switch to Other Type of SysDC 5-3 Max of Contiguous Read SysDC Before Switch to Other Type of SysDC 2-0 Max of Contiguous Write SysDC Before Switch to Other Type of SysDC Device 0 Offset 54 - BIU Control .................................... RW 7 SDRAM Self-Refresh When Disconnected 0 Disable................................................... default 1 Enable 6 Probe Next Tag State T1 When PCI Master Read Cacheing Enabled 0 Disable................................................... default 1 Enable 5 S2K Data Input Buffer 0 Disable................................................... default 1 Enable 4 S2K Data Output Enable Timing 0 1T Setup / Hold ..................................... default 1 1/2T Setup / Hold 3 DRAM Speculative Read for PCI Master Read (Before Probe Result is Known) 0 Disable................................................... default 1 Enable 2 PCI Master Pipeline Request 0 Disable................................................... default 1 Enable 1 PCI-to-CPU / CPU-to-PCI (P2C / C2P) Concurrency 0 Disable................................................... default 1 Enable 0 Fast Write-to-Read Turnaround 0 Disable................................................... default 1 Enable Device 0 Configuration Registers - Host Bridge These registers are normally programmed once at system initialization time. Host CPU Control Device 0 Offset 50 - S2K Timing Control I.....................RW The contents of this register are preserved during suspend. Bits 5-0 have no default value. When the system is first powered up, S2K timing (SIP) is determined by an internal ROM. After power up, the user can change the timing (the SIP) by programming SDCout, SDCin,.Dinit, Ainit, and MuxPreLd, then setting bit-7 of this register, then generating a system reset by programming SB. 7 6 5-4 3-0 Disable ROM Table 0 Read SDCout, SDCin, Dinit, Ainit, MuxPreLd, and WrDataDly values from internal ROM .....................................................default 1 Normal read of SDCout, SDCin, Dinit, Ainit, MuxPreLd, and WrDataDly values from fields of registers Rx50-52 ........................................ always reads 0 Reserved Read Data Delay (SDCOutDelay)............. (SDCout) Write Data Delay (SDCInDelay) ................ (SDCin) Device 0 Offset 51 - S2K Timing Control II ...................RW The contents of this register are preserved during suspend. The fields in this register have no default value. 7-6 5-4 3 2-0 North Bridge Data Receiver Mux Initial Count...... .....................................................(Dinit) North Bridge Address Receiver Mux Initial Count .....................................................(Ainit) ........................................ always reads 0 Reserved CPU Data / Address Mux Preload Count ................ ............................................(MuxPreLd) 1 Device 0 Offset 52 - S2K Timing Control III..................RW The contents of this register are preserved during suspend. Bits 2-0 have no default value. 2-0 Preliminary Revision 0.1, October 9, 2000 7 6 5-4 3 Disconnect Enable When STPGNT Detected Write to Read Delay ................................ default = 1 Read to Write Delay ............................ default = 11b 1ns Skew Between Even / Odd Clock Group For Data (Strapped from MAB3) 0 Disable .................default if no strap on MAB3 1 Enable Write Data Delay from SYSDC to CPU Data .......................................... (WrDataDly) Output 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -24- Device 0 Offset 55 - Debug .............................................. RW 7-0 Reserved (do not program)......................default = 0 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 5F-5A - DRAM Row Ending Address: Offset 5A - Bank 0 Ending (HA[31:24]) (01h) .......... RW Offset 5B - Bank 1 Ending (HA[31:24]) (01h) .......... RW Offset 5C - Bank 2 Ending (HA[31:24]) (01h) .......... RW Offset 5D - Bank 3 Ending (HA[31:24]) (01h) .......... RW Offset 5E - Bank 4 Ending (HA[31:24]) (01h) .......... RW Offset 5F - Bank 5 Ending (HA[31:24]) (01h) .......... RW Note : BIOS is required to fill the ending address registers for all banks even if no memory is populated. The endings have to be in incremental order. Device 0 Offset 60 - DRAM Type (00h).......................... RW 7-6 DRAM Type for Bank 7/6 00 -reserved- ............................................... default 01 -reserved10 -reserved11 SDRAM 5-4 DRAM Type for Bank 5/4........................default=00 3-2 DRAM Type for Bank 3/2........................default=00 1-0 DRAM Type for Bank 1/0........................default=00 DRAM Control These registers are normally set at system initialization time and not accessed after that during normal system operation. Some of these registers, however, may need to be programmed using specific sequences during power-up initialization to properly detect the type and size of installed memory (refer to the VIA Technologies VT8363A BIOS porting guide for details). Table 5. System Memory Map Space Start DOS 0 VGA 640K BIOS 768K BIOS 784K BIOS 800K BIOS 816K BIOS 832K BIOS 848K BIOS 864K BIOS 880K BIOS 896K BIOS 960K Sys 1MB Bus D Top Init 4G-64K Size 640K 128K 16K 16K 16K 16K 16K 16K 16K 16K 64K 64K -- Address Range 00000000-0009FFFF 000A0000-000BFFFF 000C0000-000C3FFF 000C4000-000C7FFF 000C8000-000CBFFF 000CC000-000CFFFF 000D0000-000D3FFF 000D4000-000D7FFF 000D8000-000DBFFF 000DC000-000DFFFF 000E0000-000EFFFF 000F0000-000FFFFF 00100000-DRAM Top DRAM Top-FFFEFFFF 64K FFFEFFFF-FFFFFFFF Comment Cacheable Used for SMM Shadow Ctrl 1 Shadow Ctrl 1 Shadow Ctrl 1 Shadow Ctrl 1 Shadow Ctrl 2 Shadow Ctrl 2 Shadow Ctrl 2 Shadow Ctrl 2 Shadow Ctrl 3 Shadow Ctrl 3 Can have hole 0 (+ & ' ' 3 0 7 6+ +4 # ' . & 000Fxxxx alias MA: 16Mb (0xx) 64/128Mb (100) 2/4 bank 256Mb (101) 2/4B 256Mb (110) 2/4B 256Mb (111) 2/4B 14 13 12 11 11 11 24 13 12 27/ 13 12 24 25 24 13 12 28 13 12 26 24 13 12 28 13 12 27 24 13 12 28 13 12 10 9 8 22 21 20 PC 24 23 22 21 20 PC 26 25 7 19 10 19 10 6 18 9 18 9 5 17 8 17 8 4 16 7 16 7 3 15 6 15 6 22 21 20 19 18 17 8 22 21 20 19 18 17 PC 26 25 10 9 8 22 21 20 19 18 17 PC 26 25 10 9 8 PC 26 25 10 9 Table 6. Memory Address Mapping Table 2 14 5 14 5 14 5 14 5 14 5 1 13 4 11 4 11 4 11 4 11 4 0 12 3 23 3 23 3 23 3 23 3 11x10, 11x9, 11x8 x4: 14x10 x8: 14x9 x32: 14x8 x16: 14x9 x8: 14x10 x4: 14x11 Device 0 Offset 59-58 - DRAM MA Map Type (0040h).RW 15-13 Bank 5/4 MA Map Type (see below) 12 Bank 5/4 Virtual Channel Enable................... def=0 11-8 Reserved 7-5 .................................................... def = 0 4 3-1 0 Bank 3/2 MA Map Type (see above) Bank 3/2 Virtual Channel Enable................... def=0 Preliminary Revision 0.1, October 9, 2000 Bank 1/0 MA Map Type 000 16Mbit SDRAM.....................................default 001 -reserved01x -reserved100 64Mbit / 128Mbit SDRAM 101 256Mbit x 32 SDRAM 110 256Mbit x 16 SDRAM 111 256Mbit x 8 or x 4 SDRAM Bank 1/0 Virtual Channel Enable................... def=0 16 7 16 7 16 7 15 6 15 6 15 6 "PC" = "Precharge Control" (refer to SDRAM specifications) 1 -25- Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 63 - Shadow RAM Control 3 (00h) ....... RW 7-6 E0000h-EFFFFh 00 Read/write disable ................................. default 01 Write enable 10 Read enable 11 Read/write enable 5-4 F0000h-FFFFFh 00 Read/write disable ................................. default 01 Write enable 10 Read enable 11 Read/write enable 3-2 Memory Hole 00 None .................................................... default 01 512K-640K 10 15M-16M (1M) 11 14M-16M (2M) 1 A,BK Direct SMRAM Access 0 Enable ................................................... default 1 Disable 0 A,BK DRAM Access 0 Disable................................................... default 1 Enable Preliminary Revision 0.1, October 9, 2000 Device 0 Offset 62 - Shadow RAM Control 2 (00h) .......RW 7-6 DC000h-DFFFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 5-4 D8000h-DBFFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 3-2 D4000h-D7FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 1-0 D0000h-D3FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -26- Device 0 Offset 61 - Shadow RAM Control 1 (00h) .......RW 7-6 CC000h-CFFFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 5-4 C8000h-CBFFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 3-2 C4000h-C7FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 1-0 C0000h-C3FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable Device 0 Offset 64 - DRAM Timing for Banks 0,1 (ECh)RW Device 0 Offset 65 - DRAM Timing for Banks 2,3 (ECh)RW Device 0 Offset 66 - DRAM Timing for Banks 4,5 (ECh)RW Settings for Registers 67-64 7 Precharge Command to Active Command Period 0 TRP = 2T 1 TRP = 3T ............................................... default 6 Active Command to Precharge Command Period 0 TRAS = 5T 1 TRAS = 6T ............................................. default 5-4 CAS Latency 00 1T 01 2T 10 3T ...................................... default 11 reserved 3 DIMM Type 0 Standard 1 Registered ............................................. default 2 SDRAM: ACTIVE Command to CMD Command 0 2T 1 3T .................................................... default 2 VCM SDRAM: Prefetch Read Latency 0 4T 1 3T .................................................... default 1-0 Bank Interleave 00 No Interleave ......................................... default 01 2-way 10 4-way 11 Reserved 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 69 - DRAM Clock Select (00h) ............. RW ........................................always reads 0 7 Reserved 6 DRAM Operating Frequency Faster Than CPU 0 DRAM Same As or Equal to CPU......... default 1 DRAM Faster Than CPU by 33 MHz Rx68[0] 0 0 1 1 5 Rx69[6] 0 1 0 1 CPU / DRAM 100 / 100 100 / 133 133 / 133 (def) -reserved- Note: See also Rx69[6] Note: PCI and AGP bus frequencies are 33 and 66 MHz respectively independent of the setting of this bit Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & 4 3 2 1 0 -27- Device 0 Offset 68 - DRAM Control (00h) ......................RW ........................................ always reads 0 7 Reserved 6 Bank Page Control 0 Allow only pages of the same bank active.. def. 1 Allow pages of different banks to be active ........................................ always reads 0 5-3 Reserved 2 Burst Refresh 0 Disable ...................................................default 1 Enable (burst 4 times) ........................................ always reads 0 1 Reserved 0 System Frequency Divider .................................. RO Latched from MA14 at the rising edge of RESET#. 0 CPU Frequency =100 MHz (200 MHz FSB) ............................................ .....no strap default 1 CPU Frequency =133 MHz (266 MHz FSB) Write Recovery Time For Write With AutoPrecharge 0 1T .................................................... default 1 2T DRAM Controller Command Register Output 0 Disable................................................... default 1 Enable Fast DRAM Precharge for Different Bank 0 Disable................................................... default 1 Enable DRAM 4K Page Enable (for 64Mbit DRAM) 0 Disable................................................... default 1 Enable DIMM Type 0 Unbuffered............................................. default 1 Registered AutoPrecharge on CPU Writeback / TLB Lookup 0 Disable................................................... default 1 Enable 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 6B - DRAM Arbitration Control (01h) RW 7-6 Arbitration Parking Policy 00 Park at last bus owner ............................ default 01 Park at CPU side 10 Park at AGP side 11 Reserved 5 Fast Read to Write turn-around 0 Disable................................................... default 1 Enable ........................................always reads 0 4 Reserved 3 MD Bus Second Level Strength Control 0 Normal slew rate control........................ default 1 More slew rate control 2 CAS Bus Second Level Strength Control 0 Normal slew rate control........................ default 1 More slew rate control 1 AGP Pad Slew Rate Control 0 Disable................................................... default 1 Enable 0 Multi-Page Open 0 Disable (page registers marked invalid and no page register update which causes non pagemode operation) 1 Enable ................................................... default Device 0 Offset 6A - Refresh Counter (00h)....................RW 7-0 Refresh Counter (in units of 16 CPUCLKs) 00 DRAM Refresh Disabled .......................default 01 32 CPUCLKs 02 48 CPUCLKs 03 64 CPUCLKs 04 80 CPUCLKs 05 96 CPUCLKs ...... The programmed value is the desired number of 16CPUCLK units minus one. Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -28- 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 6D - DRAM Drive Strength (00h)......... RW 7 ESDRAM Memory Type 0 Disable................................................... default 1 Enable 6-5 Delay DRAM Read Latch 00 No Delay................................................ default 01 0.5 ns 10 1.0 ns 11 1.5 ns 4 Memory Data Drive (MD, MECC) 0 6 mA .................................................... default 1 8 mA 3 SDRAM Command Drive (SRAS#, SCAS#, SWE#) 0 16mA .................................................... default 1 24mA 2 Memory Address Drive (MA, WE#) 0 16mA .................................................... default 1 24mA 1 CAS# Drive 0 8 mA .................................................... default 1 12 mA 0 RAS# Drive 0 16mA .................................................... default 1 24mA Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -29- Device 0 Offset 6C - SDRAM Control (00h) ...................RW 7 MA Control .............................................. default = 0 6 SRASA / SCASA / SWEA Control ......... default = 0 ........................................ always reads 0 5-4 Reserved 3 Fast TLB Lookup 0 Disable ...................................................default 1 Enable 2-0 SDRAM Operation Mode Select 000 Normal SDRAM Mode ..........................default 001 NOP Command Enable 010 All-Banks-Precharge Command Enable (CPU-to-DRAM cycles are converted to All-Banks-Precharge commands). 011 MSR Enable CPU-to-DRAM cycles are converted to commands and the commands are driven on MA[14:0]. The BIOS selects an appropriate host address for each row of memory such that the right commands are generated on MA[14:0]. 100 CBR Cycle Enable (if this code is selected, CAS-before-RAS refresh is used; if it is not selected, RAS-Only refresh is used) 101 Reserved 11x Reserved 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A PCI Bus Control These registers are normally programmed once at system initialization time. Device 0 Offset 70 - PCI Buffer Control (00h)................RW 7 CPU to PCI Post-Write 0 Disable ...................................................default 1 Enable 6 PCI Master to DRAM Post-Write 0 Disable ...................................................default 1 Enable ........................................ always reads 0 5 Reserved 4 PCI Master to DRAM Prefetch 0 Disable ...................................................default 1 Enable 3 Enhance CPU-to-PCI Write 0 Normal operation ...................................default 1 Reduce 1 cycle when the CPU-to-PCI buffer becomes available after being full (PCI and AGP buses) 2 PCI Master Read Caching 0 Disable ...................................................default 1 Enable 1 Delay Transaction 0 Disable ...................................................default 1 Enable 0 Slave Device Stopped Idle Cycle Reduction 0 Normal Operation...................................default 1 Reduce 1 PCI idle cycle when stopped by a slave device (PCI and AGP buses) Device 0 Offset 71 - CPU to PCI Flow Control 1 (00h) . RW 7 Dynamic Burst 0 Disable................................................... default 1 Enable (see note under bit-3 below) 6 Byte Merge 0 Disable................................................... default 1 Enable ........................................always reads 0 5 Reserved 4 PCI I/O Cycle Post Write 0 Disable................................................... default 1 Enable 3 PCI Burst 0 Disable................................................... default 1 Enable (bit7=1 will override this option) bit-7 bit-3 Operation 0 0 Every write goes into the write buffer and no PCI burst operations occur. 0 1 If the write transaction is a burst transaction, the information goes into the write buffer and burst transfers are later performed on the PCI bus. If the transaction is not a burst, PCI write occurs immediately (after a write buffer flush). 1 x Every write transaction goes to the write buffer; burstable transactions will then burst on the PCI bus and non-burstable won't. This is the normal setting. 2 PCI Fast Back-to-Back Write 0 Disable................................................... default 1 Enable 1 Quick Frame Generation 0 Disable................................................... default 1 Enable 0 1 Wait State PCI Cycles 0 Disable................................................... default 1 Enable Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -30- 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 73 - PCI Master Control 1 (00h) ........... RW ........................................always reads 0 7 Reserved 6 PCI Master 1-Wait-State Write 0 Zero wait state TRDY# response........... default 1 One wait state TRDY# response 5 PCI Master 1-Wait-State Read 0 Zero wait state TRDY# response........... default 1 One wait state TRDY# response ........................................always reads 0 4 Reserved 3 Assert STOP# after PCI Master Write Timeout 0 Disable................................................... default 1 Enable 2 Assert STOP# after PCI Master Read Timeout 0 Disable................................................... default 1 Enable 1 LOCK# Function 0 Disable................................................... default 1 Enable 0 PCI Master Broken Timer Enable 0 Disable................................................... default 1 Enable. Force into arbitration when there is no FRAME# 16 PCICLK's after the grant. Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -31- Device 0 Offset 72 - CPU to PCI Flow Control 2 (00h) RWC 7 Retry Status 0 No retry occurred ...................................default 1 Retry occurred ......................... write 1 to clear 6 Retry Timeout Action 0 Retry Forever (record status only)..........default 1 Flush buffer for write or return all 1s for read 5-4 Retry Limit 00 Retry 2 times ..........................................default 01 Retry 16 times 10 Retry 4 times 11 Retry 64 times 3 Clear Failed Data and Continue Retry 0 Flush the entire post-write buffer ...........default 1 When data is posting and master (or target) abort fails, pop the failed data if any, and keep posting 2 CPU Backoff on PCI Read Retry Failure 0 Disable ...................................................default 1 Backoff CPU when reading data from PCI and retry fails 1 Reduce 1T for FRAME# Generation 0 Disable ...................................................default 1 Enable 0 Reduce 1T for CPU read PCI slave 0 Disable ..................................................Default 1 Enable Device 0 Offset 74 - PCI Master Control 2 (00h) ........... RW 7 PCI Master Read Prefetch by Enhance Command 0 Always Prefetch..................................... default 1 Prefetch only if Enhance command 6 Reserved (Do Not Program) ....................default = 0 ........................................always reads 0 5 Reserved 4 Dummy Request........................................default = 0 3 PCI Delay Transaction Timeout 0 Disable................................................... default 1 Enable 2 Backoff CPU Immediately on CPU-to-AGP 0 Disable................................................... default 1 Enable 1-0 CPU/PCI Master Latency Timer Control 00 AGP master reloads MLT timer ............ default 01 AGP master falling edge reloads MLT timer 10 AGP master rising edge resets timer to 00 and AGP master falling edge reloads MLT timer 11 Reserved (do not program) 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 76 - PCI Arbitration 2 (00h).................. RW 7 PCI CPU-to-PCI Post-Write Retry Failed 0 Continue retry attempt ........................... default 1 Go to arbitration 6 CPU Latency Timer Bit-0 ....................................RO 0 CPU has at least 1 PCLK time slot when CPU has PCI bus 1 CPU has no time slot 5-4 Master Priority Rotation Control 00 Disable................................................... default 01 Grant to CPU after every PCI master grant 10 Grant to CPU after every 2 PCI master grants 11 Grant to CPU after every 3 PCI master grants With setting 01, the CPU will always be granted access after the current bus master completes, no matter how many PCI masters are requesting. With setting 10, if other PCI masters are requesting during the current PCI master grant, the highest priority master will get the bus after the current master completes, but the CPU will be guaranteed to get the bus after that master completes. With setting 11, if other PCI masters are requesting, the highest priority will get the bus next, then the next highest priority will get the bus, then the CPU will get the bus. In other words, with the above settings, even if multiple PCI masters are continuously requesting the bus, the CPU is guaranteed to get access after every master grant (01), after every other master grant (10) or after every third master grant (11). 3-2 REQn# to REQ4# Mapping 00 REQ4# 01 REQ0# 10 REQ1# 11 REQ2# 1 CPU QW or High DW Read Accesses to PCI Slave Allowed To Be Backed Off 0 Disable................................................... default 1 Enable 0 REQ4# Is High Priority Master 0 Disable................................................... default 1 Enable Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -32- Device 0 Offset 75 - PCI Arbitration 1 (00h) ..................RW 7 Arbitration Mechanism 0 PCI has priority ......................................default 1 Fair arbitration between PCI and CPU 6 Arbitration Mode 0 REQ-based (arbitrate at end of REQ#)...default 1 Frame-based (arbitrate at FRAME# assertion) 5-4 Latency Timer ........... read only, reads Rx0D bits 2:1 3-0 PCI Master Bus Time-Out (force into arbitration after a period of time) 0000 Disable ...................................................default 0001 1x32 PCICLKs 0010 2x32 PCICLKs 0011 3x32 PCICLKs 0100 4x32 PCICLKs ... ... 1111 15x32 PCICLKs 1 Device 0 Offset 77 - Chip Test Mode (00h)..................... RW 7-0 Reserved (do not use) .................................default=0 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 7A - Miscellaneous Control (00h)......... RW 7 No Time-Out Arbitration for Consecutive Frame Accesses 0 Enable .................................................... default 1 Disable ........................................always reads 0 6-5 Reserved 4 Invalidate PCI / AGP Buffered (Cached) Read Data for CPU to PCI / AGP Accesses 0 Disable................................................... default 1 Enable 3 Background PCI-to-PCI Write Cycle Mode 0 Disable................................................... default 1 Enable ........................................always reads 0 2-1 Reserved 0 South Bridge PCI Master Force Timeout When PCI Master Occupancy Timer Is Up 0 Disable................................................... default 1 Enable Device 0 Offset 7B - PCI Master Access Control (00h) RW ........................................always reads 0 7-2 Reserved 1 PCI Master Access Head / Tail Select 0 Tail .................................................... default 1 Head ........................................always reads 0 0 Reserved Device 0 Offset 79 - PMU Control 2 (00h) ......................RW ........................................ always reads 0 7-3 Reserved 2 Indicate SIO Request to DRAM Controller 0 Disable ...................................................default 1 Enable ........................................ always reads 0 1 Reserved 0 2T Rate Snoop Write Enable To Invalidate Read Data Caching Support 0 Disable ...................................................default 1 Enable Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -33- Device 0 Offset 78 - PMU Control I (00h).......................RW 7 I/O Port 22 Access 0 CPU access to I/O address 22h is passed on to the PCI bus .............................................default 1 CPU access to I/O address 22h is processed internally 6 Suspend Refresh Type 0 CBR Refresh ..........................................default 1 Self Refresh ........................................ always reads 0 5 Reserved 4 Dynamic Clock Control 0 Normal (clock is always running)...........default 1 Clock to various internal functional blocks is disabled when those blocks are not being used ........................................ always reads 0 3 Reserved 2 GSTOP# Assertion 0 Disable (GSTOP# is always high)..........default 1 Enable (GSTOP# could be low) ........................................ always reads 0 1 Reserved 0 Memory Clock Enable (CKE) Function 0 CKE Function Disable............................default 1 CKE Function Enable Device 0 Offset 7E - DLL/PLL Test Mode 1 (00h) ........ RW 7-0 Reserved (do not use) .................................default=0 Device 0 Offset 7F - DLL/PLL Test Mode 2 (00h) ........ RW 7-0 Reserved (do not use) .................................default=0 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A GART / Graphics Aperture Control The function of the Graphics Address Relocation Table (GART) is to translate virtual 32-bit addresses issued by an AGP device into 4K-page based physical addresses for system memory access. In this translation, the upper 20 bits (A31A12) are remapped, while the lower 12 address bits (A11-A0) are used unchanged. A one-level fully associative lookup scheme is used to implement the address translation. In this scheme, the upper 20 bits of the virtual address are used to point to an entry in a page table located in system memory. Each page table entry contains the upper 20 bits of a physical address (a "physical page" address). For simplicity, each page table entry is 4 bytes. The total size of the page table depends on the GART range (called the "aperture size") which is programmable in the VT8363A. This scheme is shown in the figure below. 31 Since address translation using the above scheme requires an access to system memory, an on-chip cache (called a "Translation Lookaside Buffer" or TLB) is utilized to enhance performance. The TLB in the VT8363A contains 16 entries. Address "misses" in the TLB require an access of system memory to retrieve translation data. Entries in the TLB are replaced using an LRU (Least Recently Used) algorithm. Addresses are translated only for accesses within the "Graphics Aperture" (GA). The Graphics Aperture can be any power of two in size from 1MB to 256MB (i.e., 1MB, 2MB, 4MB, 8MB, etc). The base of the Graphics Aperture can be anywhere in the system virtual address space on an address boundary determined by the aperture size (e.g., if the aperture size is 4MB, the base must be on a 4MB address boundary). The Graphics Aperture Base is defined in register offset 10 of device 0. The Graphics Aperture Size and TLB Table Base are defined in the following register group (offsets 84 and 88 respectively) along with various control bits. Virtual Page Address TLB Base Page Table 31 Physical Page Address Figure 4. Graphics Aperture Address Translation Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & 12 11 0 Page Offset index 12 11 0 Page Offset 1 -34- Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset 84 - Graphics Aperture Size (00h) ........ RW 7-0 Graphics Aperture Size 11111111 1M 11111110 2M 11111100 4M 11111000 8M 11110000 16M 11100000 32M 11000000 64M 10000000 128M 00000000 256M Offset 8B-88 - GA Translation Table Base (00000000h) RW 31-12 Graphics Aperture Translation Table Base. Pointer to the base of the translation table in system memory used to map addresses in the aperture range (the pointer to the base of the "Directory" table). ........................................always reads 0 11-3 Reserved 2 One Cycle TLB Flush 0 Disable................................................... default 1 Enable 1 Graphics Aperture Enable 0 Disable................................................... default 1 Enable Note: To disable the Graphics Aperture, set this bit to 0 and set all bits of the Graphics Aperture Size to 0. To enable the Graphics Aperture, set this bit to 1 and program the Graphics Aperture Size to the desired aperture size. ........................................always reads 0 0 Reserved Device 0 Offset 83-80 - GART/TLB Control (00000000h) RW ........................................ always reads 0 31-16 Reserved 15 14 13 12 11 10 9 8 7 Page TLB Bank Test Data 1 (AND Function) ...RO Page TLB Bank Test Data 0 (OR Function) ......RO Page LRU Parity ..................................................RO GART TLB LRU Parity ......................................RO GART TLB Test Data 1 (AND Function) ..........RO GART TLB Test Data 0 (OR Function).............RO Page TLB Test Data 1 (AND Function) .............RO Page TLB Test Data 0 (OR Function) ................RO Flush Page TLB 0 Disable ...................................................default 1 Enable Reserved (always program to 0) ........................ RW 6-4 3 2 1 0 PCI Master Address Translation for GA Access 0 Addresses generated by PCI Master accesses of the Graphics Aperture will not be translated .....................................................default 1 PCI Master GA addresses will be translated AGP Master Address Translation for GA Access 0 Addresses generated by AGP Master accesses of the Graphics Aperture will not be translated .....................................................default 1 AGP Master GA addresses will be translated CPU Address Translation for GA Access 0 Addresses generated by CPU accesses of the Graphics Aperture will not be translated ..... def 1 CPU GA addresses will be translated AGP Address Translation for GA Access 0 Addresses generated by AGP accesses of the Graphics Aperture will not be translated ..... def 1 AGP GA addresses will be translated Preliminary Revision 0.1, October 9, 2000 1 Note: For any master access to the Graphics Aperture range, snoop will not be performed. 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -35- Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A AGP Control Device 0 Offset A3-A0 - AGP Capability Identifier (0020C002h) ..........................................................RO ...................................... always reads 00 31-24 Reserved 23-20 Major Specification Revision ... always reads 0010b Major rev # of AGP spec that device conforms to 19-16 Minor Specification Revision ... always reads 0000b Minor rev # of AGP spec that device conforms to 15-8 Pointer to Next Item........always reads C0 (last item) .. (always reads 02 to indicate it is AGP) 7-0 AGP ID Device 0 Offset AB-A8 - AGP Command (00000000h) . RW 31-24 Request Depth (reserved for target) .. always reads 0s ...................................... always reads 0s 23-10 Reserved 9 SideBand Addressing Enable 0 Disable................................................... default 1 Enable 8 AGP Enable 0 Disable................................................... default 1 Enable ...................................... always reads 0s 7-6 Reserved 5 4G Enable 0 Disable................................................... default 1 Enable 4 Fast Write Enable 0 Disable................................................... default 1 Enable ...................................... always reads 0s 3 Reserved 2 4X Mode Enable 0 Disable................................................... default 1 Enable 1 2X Mode Enable 0 Disable................................................... default 1 Enable 0 1X Mode Enable 0 Disable................................................... default 1 Enable Device 0 Offset A7-A4 - AGP Status (1F000203h) ..........RO 31-24 Maximum AGP Requests ............ always reads 1Fh Max # of AGP requests the device can manage (32) See also RxFC[1] and RxFD[4-0] .......................................always reads 0s 23-10 Reserved 9 Supports SideBand Addressing ........ always reads 1 .......................................always reads 0s 8-6 Reserved 5 4G Supported ..................(can be written at RxAE[5] 4 Fast Write Supported .....(can be written at RxAE[4] .......................................always reads 0s 3 Reserved 2 4X Rate Supported........ (can be written at RxAE[2]) 1 2X Rate Supported........ (can be written at RxAC[3]) 0 1X Rate Supported............................. always reads 1 Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -36- 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset AD - AGP Latency Timer (02h) ........... RW ........................................always reads 0 7 Reserved 6 AGP Data / Strobe Input Buffer 0 Disable................................................... default 1 Enable 5 Hold Last GD Output Data 0 Disable................................................... default 1 Enable 4 Choose First or Last Ready of DRAM 0 Last ready chosen .................................. default 1 First ready chosen 3-0 AGP Data Phase Latency Timer ......... default = 02h Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -37- Device 0 Offset AC - AGP Control (00h) ........................RW ........................................ always reads 0 7 Reserved 6 CPU Stall on AGP Command FIFO GART Address Request 0 Disable ...................................................default 1 Enable 5 AGP Read Snoop DRAM Post-Write Buffer 0 Disable ...................................................default 1 Enable 4 GREQ# Priority Becomes Higher When Arbiter is Parked at AGP Master 0 Disable ...................................................default 1 Enable 3 2X Rate Supported (read also at RxA4[1]) 0 Not supported ........................................default 1 Supported 2 LPR In-Order Access (Force Fence) 0 Fence/Flush functions not guaranteed. AGP read requests (low/normal priority and high priority) may be executed before previously issued write requests...............................default 1 Force all requests to be executed in order (automatically enables Fence/Flush functions). Low (i.e., normal) priority AGP read requests will never be executed before previously issued writes. High priority AGP read requests may still be executed prior to previously issued write requests as required. 1 AGP Arbitration Parking 0 Disable ...................................................default 1 Enable (GGNT# remains asserted until either GREQ# de-asserts or data phase ready) 0 AGP to PCI Master or CPU to PCI Turnaround Cycle 0 2T or 3T Timing.....................................default 1 1T Timing Device 0 Offset AE - AGP Miscellaneous Control (00h)RW ........................................always reads 0 7-6 Reserved 5 Greater Than 4GB Supported 0 Disable................................................... default 1 Enable 4 Fast Write Supported 0 Fast Write not supported........................ default 1 Fast Write supported ........................................always reads 0 3 Reserved 2 4x Rate Supported 0 4x Rate not supported ............................ default 1 4x Rate supported ........................................always reads 0 1-0 Reserved Device 0 Offset AF - AGP Strobe Drive Strength ......... RW 7-4 AGP Strobe Output Buffer Drive Strength N Ctrl 3-0 AGP Strobe Output Buffer Drive Strength P Ctrl 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset B2 - AGP Pad Drive / Delay Control ... RW 7 GD/GBE/GDS, SBA/SBS Control 1.5V (Bit-1 = 0) 0 SBA/SBS = no cap ............................... default GD/GBE/GDS = no cap 1 SBA/SBS = no cap GD/GBE/GDS = cap 3.3V (Bit-1 = 1) 0 SBA/SBS = cap .................................... default GD/GBE/GDS = no cap 1 SBA/SBS = cap GD/GBE/GDS = cap ........................................always reads 0 6 Reserved 5 S2K Slew Rate Control .....strapped from SRASA# 0 Enable .................................................... default 1 Disable 4 GD[31-16] Staggered Delay 0 None .................................................... default 1 GD[31:16] delayed by 1 ns ........................................always reads 0 3 Reserved 2 AGP Preamble Control 0 Disable................................................... default 1 Enable 1 AGP Voltage 0 1.5V .................................................... default 1 3.3V 0 GDS Output Delay 0 None .................................................... default 1 GDS[1-0] & GDS[1-0]# delayed by 0.4 ns (GDS1 & GDS1# will be delayed an additional 1ns if bit-4 = 1) Device 0 Offset B0 - AGP Pad Control / Status (8xh)....RW 7 AGP Strobe VREF Control 0 STB VREF is STB# and vice versa 1 STB VREF is AGPREF ........................default 6 AGP 4x Strobe & GD Pad Drive Strength 0 Drive strength set to compensation circuit default.....................................................default 1 Drive strength controlled by RxB1[7-0] 5-3 AGP Compensation Circuit N Control Output .RO 2-0 AGP Compensation Circuit P Control Output .RO Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -38- Device 0 Offset B1 - AGP Drive Strength (63h).............RW 7-4 AGP Output Buffer Drive Strength N Ctrl ... def=6 3-0 AGP Output Buffer Drive Strength P Ctrl.... def=3 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset B4 - S2K Compensation Strapping.......RW 7 Internal Pullup Strength Select 0 Per strapping on MA[13-12] (see bits 5-4).. def 1 Auto Mode ........................................ always reads 0 6 Reserved 5-4 Internal Pullup Strength set from MA[13-12] straps 00 Strapping Mode .......................no strap default 01 Strapping Mode 10 Strapping Mode 11 Auto Mode 3 Output Drive Strength Select 0 Per strapping on MA[10-9] (see bits 1-0).... def 1 Auto Mode ........................................ always reads 0 2 Reserved 1-0 Output Drive Strength .... set from MA[10-9] strap 00 Auto Mode ............................... no strap default 01 Strapping Mode 10 Strapping Mode 11 Strapping Mode Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -39- Device 0 Offset B3 - CPU Strapping Control..................RO Device 0 Offset B5 - S2K Compensation Result 1 .......... RO 7-3 CPU Clock Division .. 4 lsbs set from MA3-0 straps 7-4 Pullup Autocompensation Result ............default = 0 00000 11 ................................................................ no strap default 3-0 Pulldown Autocompensation Result .......default = 0 00001 11.5 Device 0 Offset B6 - S2K Compensation Result 2 .......... RO 00010 12 7 S2K Edge DQ Mode ...............set from MA11 strap 00011 12.5 0 Central DQ............................................. default 00100 5 1 Edge DQ 00101 5.5 ........................................always reads 0 6-5 Reserved 00110 6 4-0 S2K Strobe Delay (EdgeDQ) .................................... 00111 6.5 ...................... set from MA[8-4] straps 01000 7 0 Auto Mode............................... no-strap default 01001 7.5 ~0 Strapping Mode 01010 8 01011 8.5 Device 0 Offset B7 - S2K Compensation Result 3 .......... RO 01100 9 ........................................always reads 0 7-5 Reserved 01101 9.5 4-0 S2K Strobe Delay from DLL Counter (Auto) 01110 10 ..............................................default = 0 01111 10.5 10000 3 Device 0 Offset B8 - S2K Compensation Result 4 .......... RO 10001 3.5 7 S2K Compensation Circuit Trigger 10010 4 6 DLL Autodetect ................................................... RO 10011 4.5 5 Delay Compensation Counter Control 101xx -reserved4-3 S2K Pad AC Coupling to VREF Signal in Address 2 S2K Compensation Drive Strength / Data Output Clock 0 Strap .....................................................default 2-0 S2K Pad Slew Rate Ctrl (7h is strongest) .... def=7h 1 Auto Calculate 1 Fast Address Out Decode .......... set from ROMSIP, otherwise 0 0 Normal .....................................no strap default 1 Fast 0 S2K Compensation Circuit 0 Enable on Reset......................................default 1 Enable on Disconnect 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 0 Offset F0 - BIOS Scratch Register 0 ............... RW 7-0 No hardware function ..............................default = 0 Device 0 Offset F1 - BIOS Scratch Register 1 ............... RW 7-0 No hardware function ..............................default = 0 Device 0 Offset F2 - BIOS Scratch Register 2 ............... RW 7-0 No hardware function ..............................default = 0 Device 0 Offset F3 - BIOS Scratch Register 3 ............... RW 7-0 No hardware function ..............................default = 0 Device 0 Offset F4 - BIOS Scratch Register 4 ............... RW 7-0 No hardware function ..............................default = 0 Device 0 Offset F5 - BIOS Scratch Register 5 ............... RW 7-0 No hardware function ..............................default = 0 Device 0 Offset F6 - Revision ID Backdoor ................... RW 7-0 Revision ID Rx8 ........................................default = 0 Device 0 Offset F7 - Foundry ID..................................... RW 7-0 No hardware function .............. default = foundry ID Device 0 Offset C0 - Power Management Capability IDRO 7-0 Capability ID .................................. always reads 01h Device 0 Offset C1 - Power Management New Pointer..RO 7-0 New Pointer ..........always reads 00h ("Null" Pointer) Device 0 Offset C2 - Power Mgmt Capabilities I ............RO 7-0 Power Management Capabilities.. always reads 02h Device 0 Offset C3 - Power Mgmt Capabilities II...........RO 7-0 Power Management Capabilities.. always reads 00h Device 0 Offset C4 - Power Mgmt Control / Status .......RW ........................................ always reads 0 7-2 Reserved 1-0 Power State 00 D0 .....................................................default 01 -reserved10 -reserved11 D3 Hot Device 0 Offset C5 - Power Management Status ............RO 7-0 Power Management Status............ always reads 00h Device 0 Offset C6 - PCI-to-PCI Bridge Support Ext. ...RO 7-0 P2P Bridge Support Extensions.... always reads 00h Device 0 Offset C7 - Power Management Data...............RO 7-0 Power Management Data .............. always reads 00h Device 0 Offset E0 - Miscellaneous Control (00h) .........RW 7 AGP Pad Power Down 0 Disable ...................................................default 1 Enable 6 Reserved (do not program) ....................... must be 0 5 Internal Graphics AGP/PCI Concurrent..... def = 0 4 CKE Drive Select ..................................... default = 0 3-1 Frame Buffer Bank Location .................. default = 0 0 Latch DRAM Data Using 0 Internal DRAM DCLK...........................default 1 External Feedback DRAM DCLK Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -40- Device 0 Offset F8 - DRAM Arbitration Timer (00h)... RW 7-4 AGP Timer (units of 4 DCLKs)...............default = 0 3-0 Host CPU Timer (units of 4 DCLKs)......default = 0 Device 0 Offset FC - Back Door Control 1 (00h)........... RW 7-4 Priority Timer...........................................default = 0 3-2 Probe Signal Select ...................................default = 0 1 Back-Door Max # of AGP Requests........default = 0 0 Read of RxA7 always returns a value of 11111b (32 requests) ............................. default 1 Read of RxA7 returns the value programmed in RxFD[4-0] 0 Back-Door Device ID Enable...................default = 0 0 Use Rx3-2 value for Rx3-2 readback..... default 1 Use RxFE-FF Back-Door Device ID for Rx3-2 read Device 0 Offset FD - Back-DoorControl 2 (00h) ........... RW ........................................always reads 0 7-5 Reserved 4-0 Max # of AGP Requests ...........................default = 0 00000 1 Request 00001 2 Requests 00010 3 Requests ... ... 11111 32 Requests (see also RxA7 and RxFC[1]) Device 0 Offset FF-FE - Back-Door Device ID (0000h) RW 15-0 Back-Door Device ID................................ default=00 1 Device 0 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 1 Offset 7-6 - Status (Primary Bus) (0230h) .... RWC 15 Detected Parity Error ........................always reads 0 14 Signaled System Error (SERR#) .......always reads 0 13 Signaled Master Abort 0 No abort received .................................. default 1 Transaction aborted by the master with Master-Abort (except Special Cycles) .............. ....................................... write 1 to clear 12 Received Target Abort 0 No abort received .................................. default 1 Transaction aborted by the target with TargetAbort ....................................... write 1 to clear 11 Signaled Target Abort........................always reads 0 10-9 DEVSEL# Timing 00 Fast 01 Medium....................................always reads 01 10 Slow 11 Reserved 8 Data Parity Error Detected ...............always reads 0 7 Fast Back-to-Back Capable ...............always reads 0 6 User Definable Features.....................always reads 0 5 66MHz Capable..................................always reads 1 4 Supports New Capability list.............always reads 1 ........................................always reads 0 3-0 Reserved Device 1 Offset 8 - Revision ID (00h) ............................... RO 7-0 VT8363A Chip Revision Code (00=First Silicon) Device 1 Offset 9 - Programming Interface (00h) ........... RO This register is defined in different ways for each Base/SubClass Code value and is undefined for this type of device. 7-0 Interface Identifier ...........................always reads 00 Device 1 Header Registers - PCI-to-PCI Bridge All registers are located in PCI configuration space. They should be programmed using PCI configuration mechanism 1 through CF8 / CFC with bus number of 0 and function number equal to 0 and device number equal to one. Device 1 Offset 1-0 - Vendor ID (1106h) ..........................RO 15-0 ID Code (reads 1106h to identify VIA Technologies) Device 1 Offset 3-2 - Device ID (8305h)............................RO 15-0 ID Code (reads 8305h to identify the VT8363A PCIto-PCI Bridge device) Device 1 Offset 5-4 - Command (0007h) .........................RW ........................................ always reads 0 15-10 Reserved 9 Fast Back-to-Back Cycle Enable ........................ RO 0 Fast back-to-back transactions only allowed to the same agent ........................................default 1 Fast back-to-back transactions allowed to different agents 8 SERR# Enable...................................................... RO 0 SERR# driver disabled ...........................default 1 SERR# driver enabled (SERR# is used to report parity errors if bit-6 is set). 7 Address / Data Stepping ...................................... RO 0 Device never does stepping....................default 1 Device always does stepping 6 Parity Error Response........................................RW 0 Ignore parity errors & continue ..............default 1 Take normal action on detected parity errors 5 VGA Palette Snoop (Not Supported).................. RO 0 Treat palette accesses normally ..............default 1 Don't respond to palette writes on PCI bus (10-bit decode of I/O addresses 3C6-3C9 hex) 4 Memory Write and Invalidate Command.......... RO 0 Bus masters must use Mem Write ..........default 1 Bus masters may generate Mem Write & Inval 3 Special Cycle Monitoring .................................... RO 0 Does not monitor special cycles .............default 1 Monitors special cycles 2 Bus Master .........................................................RW 0 Never behaves as a bus master 1 Enable to operate as a bus master on the primary interface on behalf of a master on the secondary interface ................................default 1 Memory Space.....................................................RW 0 Does not respond to memory space 1 Enable memory space access .................default 0 I/O Space .........................................................RW 0 Does not respond to I/O space 1 Enable I/O space access ........................default Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -41- Device 1 Offset A - Sub Class Code (04h) ........................ RO 7-0 Sub Class Code .reads 04 to indicate PCI-PCI Bridge Device 1 Offset B - Base Class Code (06h)....................... RO 7-0 Base Class Code .. reads 06 to indicate Bridge Device Device 1 Offset D - Latency Timer (00h) ......................... RO ........................................always reads 0 7-0 Reserved 1 Device 1 Offset E - Header Type (01h) ............................ RO 7-0 Header Type Code.......... reads 01: PCI-PCI Bridge Device 1 Offset F - Built In Self Test (BIST) (00h) ......... RO 7 BIST Supported...... reads 0: no supported functions 6 Start Test .......... write 1 to start but writes ignored ........................................always reads 0 5-4 Reserved 3-0 Response Code ..........0 = test completed successfully Device 1 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 1 Offset 3F-3E - PCI-to-PCI Bridge Control (0000h) .............................................................................. RW ........................................always reads 0 15-4 Reserved 3 VGA-Present on AGP 0 Forward VGA accesses to PCI Bus ....... default 1 Forward VGA accesses to AGP Bus Note: VGA addresses are memory A0000-BFFFFh and I/O addresses 3B0-3BBh, 3C0-3CFh and 3D03DFh (10-bit decode). "Mono" text mode uses B0000-B7FFFh and "Color" Text Mode uses B8000BFFFFh. Graphics modes use Axxxxh. Mono VGA uses I/O addresses 3Bx-3Cxh and Color VGA uses 3Cx-3Dxh. If an MDA is present, a VGA will not use the 3Bxh I/O addresses and B0000-B7FFFh memory space; if not, the VGA will use those addresses to emulate MDA modes. 2 Block / Forward ISA I/O Addresses 0 Forward all I/O accesses to the AGP bus if they are in the range defined by the I/O Base and I/O Limit registers (device 1 offset 1C-1D) .................................................... default 1 Do not forward I/O accesses to the AGP bus that are in the 100-3FFh address range even if they are in the range defined by the I/O Base and I/O Limit registers. ........................................always reads 0 1-0 Reserved Device 1 Offset 18 - Primary Bus Number (00h) ............RW 7-0 Primary Bus Number............................... default = 0 This register is read write, but internally the chip always uses bus 0 as the primary. Device 1 Offset 19 - Secondary Bus Number (00h).........RW 7-0 Secondary Bus Number ........................... default = 0 Note: AGP must use these bits to convert Type 1 to Type 0. Device 1 Offset 1A - Subordinate Bus Number (00h).....RW 7-0 Primary Bus Number............................... default = 0 Note: AGP must use these bits to decide if Type 1 to Type 1 command passing is allowed. Device 1 Offset 1B - Secondary Latency Timer (00h) ....RO ........................................ always reads 0 7-0 Reserved Device 1 Offset 1C - I/O Base (f0h)..................................RW 7-4 I/O Base AD[15:12].......................... default = 1111b 3-0 I/O Addressing Capability....................... default = 0 Device 1 Offset 1D - I/O Limit (00h)................................RW 7-4 I/O Limit AD[15:12] ................................ default = 0 3-0 I/O Addressing Capability....................... default = 0 Device 1 Offset 1F-1E - Secondary Status (0000h) ..........RO 15-0 Rx44[4] = 0: No Function (always reads 0) Rx44[4] = 1: Read same value as Rx7-6 (Pri Status) Device 1 Offset 21-20 - Memory Base (fff0h) ..................RW 15-4 Memory Base AD[31:20] ...................default = FFFh ........................................ always reads 0 3-0 Reserved Device 1 Offset 23-22 - Memory Limit (Inclusive) (0000h) RW 15-4 Memory Limit AD[31:20]........................ default = 0 ........................................ always reads 0 3-0 Reserved Device 1 Offset 27-26 - Prefetchable Memory Limit (0000h) ...............................................................................RW 15-4 Prefetchable Memory Limit AD[31:20] ................... .............................................. default = 0 ........................................ always reads 0 3-0 Reserved Device 1 Offset 2D-2C - Subsystem Vendor ID (0000h) RW Device 1 Offset 2F-2E - Subsystem ID (0000h) .............RW Device 1 Offset 34 - Capability Pointer (00h) .................RO 7-0 Capability Pointer.......................... always reads 00h Preliminary Revision 0.1, October 9, 2000 1 Device 1 Offset 25-24 - Prefetchable Memory Base (fff0h) RW 15-4 Prefetchable Memory Base AD[31:20]default = FFFh ........................................ always reads 0 3-0 Reserved 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -42- Device 1 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 1 Configuration Registers - PCI-to-PCI Bridge AGP Bus Control Device 1 Offset 40 - CPU-to-AGP Flow Control 1 (00h)RW 7 CPU-AGP Post Write 0 Disable ...................................................default 1 Enable 6 CPU-AGP Dynamic Burst 0 Disable ...................................................default 1 Enable 5 CPU-AGP One Wait State Burst Write 0 Disable ...................................................default 1 Enable 4 AGP to DRAM Prefetch 0 Disable ...................................................default 1 Enable 3 CPU to AGP Post Write Halt 0 Disable ...................................................default 1 Enable If set to 1, CPU-to-PCI posted cycles can be delayed for PCI master accesses (i.e., PCI master access is allowed even if the CPU-to-PCI buffer is not flushed) 2 MDA Present on AGP 0 Forward MDA accesses to AGP.............default 1 Forward MDA accesses to PCI Note: Forward despite IO / Memory Base / Limit Note: MDA (Monochrome Display Adapter) addresses are memory addresses B0000h-B7FFFh and I/O addresses 3B4-3B5h, 3B8-3BAh, and 3BFh (10-bit decode). 3BC-3BE are reserved for printers. Note: If Rx3E bit-3 is 0, this bit is a don't care (MDA accesses are forwarded to the PCI bus). 1 AGP Master Read Caching 0 Disable ...................................................default 1 Enable 0 AGP Delay Transaction 0 Disable ...................................................default 1 Enable Device 1 Offset 41 - CPU-to-AGP Flow Control 2 (00h) RW 7 Retry Status 0 No retry occurred................................... default 1 Retry Occurred ........................write 1 to clear 6 Retry Timeout Action 0 No action taken except to record status ....... def 1 Flush buffer for write or return all 1s for read 5-4 Retry Count 00 Retry 2, backoff CPU ............................ default 01 Retry 4, backoff CPU 10 Retry 16, backoff CPU 11 Retry 64, backoff CPU 3 Post Write Data on Abort 0 Flush entire post-write buffer on target-abort or master abort ....................................... default 1 Pop one data output on target-abort or masterabort 2 CPU Backoff on AGP Read Retry Timeout 0 Disable................................................... default 1 Enable ........................................always reads 0 1-0 Reserved 3E[3] 40[2] VGA MDA VGA MDA is is Pres. Pres. on on 0 PCI PCI 1 0 AGP AGP 1 1 AGP PCI Table 7. VGA/MDA Memory/IO Redirection Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & Axxxx, B0000 3Cx, B8xxx -B7FFF 3Dx 3Bx Access Access I/O I/O PCI PCI PCI PCI AGP AGP AGP AGP AGP PCI AGP PCI -43- Device 1 Offset 42 - AGP Master Control (00h) ............ RW 7 Read Prefetch for Enhance Command 0 Always Perform Prefetch ....................... default 1 Prefetch only if Enhance Command 6 AGP Master One Wait State Write 0 Disable................................................... default 1 Enable 5 AGP Master One Wait State Read 0 Disable................................................... default 1 Enable ........................................always reads 0 4 Reserved 3 AGP Delay Transaction Timeout 0 Disable................................................... default 1 Enable 2 Prefetch Disable when Delay Transaction Occurs 0 Normal operation................................... default 1 Disable prefetch when doing fast response to the previous delay transaction or doing read caching ........................................always reads 0 1 Reserved 0 Generate STOP# When AGP Master Access Crosses Cache Line Boundary 0 Disable................................................... default 1 Enable 1 Device 1 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 1 Offset 45 - Fast Write Control (72h) .............. RW 7 Force Fast Write Cycle to be QW Aligned (if Rx45[6] = 0) 0 Disable................................................... default 1 Enable 6 Merge Multiple CPU Transactions Into One Fast Write Burst Transaction 0 Disable 1 Enable ................................................... default 5 Merge Multiple CPU Write Cycles To Memory Offset 23-20 Into Fast Write Burst Cycles (if Rx45[6] = 0) 0 Disable 1 Enable ................................................... default 4 Merge Multiple CPU Write Cycles To Prefetchable Memory Offset 27-24 Into Fast Write Burst Cycles (if Rx45[6] = 0) 0 Disable 1 Enable ................................................... default ........................................always reads 0 3 Reserved 2 Fast Write Burst 4T Max (No Slave Flow Control) 0 Disable................................................... default 1 Enable 1 Fast Write Fast Back to Back 0 Disable 1 Enable ................................................... default 0 Fast Write Initial Block 1 Wait State 0 Disable................................................... default 1 Enable Rx45 CPU Write CPU Write Bits Address Address 7-4 in Mem1 in Mem2 x1xx 0000 x010 0 0 0010 0 1 x010 1 x001 0 0 x001 1 0001 1 0 x011 0 0 x011 1 x011 0 1 1000 1010 0 1 1001 1 0 Device 1 Offset 43 - AGP Master Latency Timer (00h) RW 7-4 Host to AGP Time Slot 0 Disable (no timer)...................................default 1 16 GCLKs 2 32 GCLKs ...... F 240 GCLKs 3-0 AGP Master Time Slot 0 Disable (no timer)...................................default 1 16 GCLKs 2 32 GCLKs ...... F 240 GCLKs Device 1 Offset 44 - Backdoor Register Control (00h) .RW ........................................ always reads 0 7-6 Reserved 5 Rx34 Capability Back Door 4 Reflect Rx7-6 Status in Rx1F-1E 0 Disable (Rx1F-1E always reads 0) .........default 1 Enable (Rx1F-1E reads same as Rx7-6) 3-2 Rx83[2-1] Back Door Value 1 Rx82[5] Back Door Value (Device Specific Intfc) 0 Back Door Register Enable for AGP Device ID (Rx47-46) 0 Disable ...................................................default 1 Enable Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -44- Fast Write Cycle Alignment QW aligned, burstable DW aligned, nonburstable n/a DW aligned, non-burstable QW aligned, burstable n/a QW aligned, burstable DW aligned, non-burstable n/a QW aligned, burstable QW aligned, burstable QW aligned, non-burstable QW aligned, non-burstable QW aligned, non-burstable 1 Device 1 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Device 1 Offset 80 - Capability ID (01h) ......................... RO 7-0 Capability ID .................................. always reads 01h Device 1 Offset 81 - Next Pointer (00h) ........................... RO 7-0 Next Pointer: Null.......................... always reads 00h Device 1 Offset 47-46 - PCI-to-PCI Bridge Device ID...RW 15-0 PCI-to-PCI Bridge Device ID............ default = 0000 Device 1 Offset 82 - Power Mgmt Capabilities 1 (02h) .. RO 7-6 Power Mgmt Capabilities ..................always reads 0 5 Power Mgmt Capabilities .programmed via Rx44[1] 4-0 Power Mgmt Capabilities .............. always reads 02h Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & -45- Device 1 Offset 83 - Power Mgmt Capabilities 2 (00h) .. RO 7-3 Power Mgmt Capabilities ..................always reads 0 2-1 Power Mgmt Capabilitiesprogrammed via Rx44[3-2] 0 Power Mgmt Capabilities ..................always reads 0 Device 1 Offset 84 - Power Mgmt Ctrl/Status (00h)...... RW ........................................always reads 0 7-2 Reserved 1-0 Power State 00 D0 .................................................... default 01 -reserved10 -reserved11 D3 Hot Device 1 Offset 85 - Power Mgmt Status (00h)............... RO 7-0 Power Mgmt Status ..................................default = 00 Device 1 Offset 86 - P2P Br. Support Extensions (00h) . RO 7-0 P2P Bridge Support Extensions................default = 00 Device 1 Offset 87 - Power Management Data (00h) ..... RO 7-0 Power Management Data..........................default = 00 1 Device 1 Register Descriptions 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Case operating temperature Storage temperature Input voltage Output voltage (VCC = 3.1 - 3.6V) Min 0 -55 -0.5 -0.5 Max 110 125 5.5 VCC + 0.5 Unit oC oC Volts Volts DC Characteristics TC -0-85oC, VCC=5V+/-5%, GND=0V Symbol VIL VIH VOL VOH IIL IOZ Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & Parameter Min -0.50 2.0 - Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions. Max 0.8 Unit V V Condition Input low voltage Input high voltage VCC+0.5 0.45 - Output low voltage V IOL=4.0mA Output high voltage 2.4 - V IOH=-1.0mA 0 +/-10 uA Tristate leakage current +/-20 uA 0.45 -46- Electrical Specifications 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A Power Characteristics TC -0-85oC, VCC=5V+/-5%, GND=0V Symbol Parameter ICC3 ISUS3 ITT ICCS2K ICCQ ICCQQ ICCHCK ICCMCK ICCGCK ICCS2KV ICCAGPV ICLKV ICC Power Supply Current - VCC3 Power Supply Current - VSUS3 Power Supply Current - VTT Power Supply Current - S2KVCC Power Supply Current - VCCQ Power Supply Current - VCCQQ Power Supply Current - VCCHCK Power Supply Current - VCCGCK Power Supply Current - VCCMCK Typ Max Unit mA mA mA mA mA mA mA mA uA uA W mA Condition Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Max operating frequency Power Supply Current - S2KVREF Power Supply Current - AGPVREF Power Supply Current - CLKVREF Power Dissipation AC Timing Specifications AC timing specifications provided are based on external zero-pf capacitance load. Min/max cases are based on the following table: Parameter 3.3V Power (VCC3, VSUS3, VTT, VCCHCK, VCCMCK, VCCGCK) 1.5V Power (VCCQ, VCCQQ) Case Temperature Drive strength for each output pin is programmable. See Rx6D for details. Preliminary Revision 0.1, October 9, 2000 0 (+ & ' ' 3 0 7 6+ +4 # ' . & uA 3.5 Max operating frequency Table 8. AC Timing Min / Max Conditions Min Max 3.465 85 1.575 Unit Volts Volts oC 3.135 0 1.425 1 -47- Electrical Specifications 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A MECHANICAL SPECIFICATIONS ; 5() ; 5() 97$ 5() 5() 5() & 6($7,1* 3/$1( Figure 5. Mechanical Specifications - 552-Pin Ball Grid Array Package Preliminary Revision 0.1, October 9, 2000 -48- 0 (+ & ' ' 3 0 7 6+ +4 # ' . & <<::55 7$,:$1 ///////// Y W R L $ % & ' ( ) * + - . / 0 1 3 5 7 8 9 : < $$ = Date Code Year = Date Code Week = Chip Revision = Lot Code 3,1 &251(5 $% $& $( $' $) 6 & 6 & $ 6 % 6 [ 552-Pin BGA 35x35x2.33 mm 1 JEDEC Spec MO-151 $ % & ' ( ) * + . / 0 1 3 5 7 8 9 : < $$ $% $& $' $( $) % $ ; 7<3 & Mechanical Specifications |
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